公开(公告)号：US10002825B2

公开(公告)日：2018-06-19

申请号：US15625083

申请日：2017-06-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shih-Chao Chiu ,  Chun-Hsien Lin ,  Yu-Cheng Pai ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L23/498 ,  H05K1/18 ,  H01L23/538 ,  H05K3/00 ,  H01L21/683 ,  H05K3/32 ,  H05K3/10 ,  H01L23/00 ,  H05K1/02 ,  H05K3/46 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32237 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2924/15313 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104 ,  H05K1/0231 ,  H05K1/185 ,  H05K1/186 ,  H05K1/189 ,  H05K3/0026 ,  H05K3/007 ,  H05K3/108 ,  H05K3/32 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10674 ,  H05K2201/10977 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0665

Abstract: The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives.

公开(公告)号：US09991197B2

公开(公告)日：2018-06-05

申请号：US15632669

申请日：2017-06-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chia-Cheng Chen ,  Chi-Ching Ho ,  Shao-Tzu Tang ,  Yu-Che Liu ,  Ying-Chou Tsai

IPC: H01L29/40 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L2221/68345 ,  H01L2224/05554 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48159 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49173 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/83005 ,  H01L2224/85005 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/181 ,  H01L2924/35121 ,  H01L2224/13099 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package is provided, which includes: a dielectric layer made of a material used for fabricating built-up layer structures; a conductive trace layer formed on the dielectric layer; a semiconductor chip is mounted on and electrically connected to the conductive trace layer; and an encapsulant formed over the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer. Since a strong bonding is formed between the dielectric layer and the conductive trace layer, the present invention can prevent delamination between the dielectric layer and the conductive trace layer from occurrence, thereby improving reliability and facilitating the package miniaturization by current fabrication methods.

公开(公告)号：US20170352615A1

公开(公告)日：2017-12-07

申请号：US15625083

申请日：2017-06-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shih-Chao Chiu ,  Chun-Hsien Lin ,  Yu-Cheng Pai ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L23/498 ,  H01L23/538 ,  H05K3/32 ,  H05K3/00 ,  H05K1/18 ,  H01L21/683 ,  H05K3/46 ,  H01L23/00 ,  H01L23/31 ,  H05K1/02 ,  H05K3/10

CPC classification number: H01L23/49838 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32237 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2924/15313 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104 ,  H05K1/0231 ,  H05K1/185 ,  H05K1/186 ,  H05K1/189 ,  H05K3/0026 ,  H05K3/007 ,  H05K3/108 ,  H05K3/32 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10674 ,  H05K2201/10977 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0665

Abstract: The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives.

公开(公告)号：US20170301658A1

公开(公告)日：2017-10-19

申请号：US15636217

申请日：2017-06-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Cheng Pai ,  Chun-Hsien Lin ,  Shih-Chao Chiu ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L25/10 ,  H01L21/48 ,  H01L23/13 ,  H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/16 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/1533 ,  H05K1/111 ,  H05K3/4697 ,  H05K2201/10674

Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a dielectric layer on the carrier; forming a plurality of conductive posts in the dielectric layer; and forming a cavity in the dielectric layer to expose the bonding pads, wherein the conductive posts are positioned around a periphery of the cavity, thereby simplifying the fabrication process.

公开(公告)号：US09735080B2

公开(公告)日：2017-08-15

申请号：US14876404

申请日：2015-10-06

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shih-Chao Chiu ,  Chun-Hsien Lin ,  Yu-Cheng Pai ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/49861 ,  H01L21/4846 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A single-layer wiring package substrate and a method of fabricating the same are provided, the method including: forming on a carrier a wiring layer having a first surface and a second surface opposing the first surface and being in contact with the carrier; forming on the carrier and on the wiring layer a dielectric body that has a first side having a first opening, from which a portion of the wiring layer is exposed, and a second side opposing the first side and disposed at the same side as the second surface of the wiring layer; and removing the carrier, with the second side of the dielectric body and the second surface of the wiring layer exposed. Therefore, a coreless package substrate is fabricated, and the overall thickness and cost of the substrate are reduced.

公开(公告)号：US20140091462A1

公开(公告)日：2014-04-03

申请号：US13729963

申请日：2012-12-28

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chia-Cheng Chen ,  Chi-Ching Ho ,  Shao-Tzu Tang ,  Yu-Che Liu ,  Ying-Chou Tsai

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L2221/68345 ,  H01L2224/05554 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48159 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49173 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/83005 ,  H01L2224/85005 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/181 ,  H01L2924/35121 ,  H01L2224/13099 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package is provided, which includes: a dielectric layer made of a material used for fabricating built-up layer structures; a conductive trace layer formed on the dielectric layer; a semiconductor chip is mounted on and electrically connected to the conductive trace layer; and an encapsulant formed over the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer. Since a strong bonding is formed between the dielectric layer and the conductive trace layer, the present invention can prevent delamination between the dielectric layer and the conductive trace layer from occurrence, thereby improving reliability and facilitating the package miniaturization by current fabrication methods.

Abstract translation: 提供一种半导体封装，其包括：由用于制造积层层结构的材料制成的电介质层; 形成在电介质层上的导电迹线层; 半导体芯片安装在导电迹线层上并电连接到导电迹线层上; 以及形成在电介质层上以封装半导体芯片和导电迹线层的密封剂。 由于在电介质层和导电迹线层之间形成牢固的接合，因此本发明能够防止电介质层与导电迹线层之间的分层发生，从而提高可靠性，并且通过现有的制造方法便于封装小型化。