公开(公告)号：US20230325574A1

公开(公告)日：2023-10-12

申请号：US18333159

申请日：2023-06-12

Applicant: Tokyo Electron Limited

Inventor： Lars Liebmann

IPC: G06F30/392 ,  G03F1/70

CPC classification number: G06F30/392 ,  G03F1/70

Abstract: In an embodiment, a method includes: receiving data representative of an electrical circuit including an arrangement of devices, inputs, outputs, and power sources; determining a minimum number of segments based on the received data; grouping the devices into N segments based on common features shared between two or more of the devices, where N is equal to the minimum number of segments; and generating discrete portions of the grouped devices to form a physical layout representative of a physical manifestation of the electrical circuit, such that when the discrete portions are integrated together they form a physical manifestation of the electrical circuit.

公开(公告)号：US20220375921A1

公开(公告)日：2022-11-24

申请号：US17880321

申请日：2022-08-03

Applicant: Tokyo Electron Limited

Inventor： Lars Liebmann ,  Jeffrey Smith ,  Daniel Chanemougame ,  Anton deVilliers

IPC: H01L27/02 ,  H01L27/06

Abstract: An integrated circuit includes an array of unit cells, each unit cell of which including field effect transistors arranged in a stack. Local interconnect structures form select conductive paths between select terminals of the field effect transistors to define cell circuitry that is confined within each unit cell. An array of contacts is disposed on an accessible surface of the unit cell, where each contact is electrically coupled to a corresponding electrical node of the cell circuitry.

公开(公告)号：US11437376B2

公开(公告)日：2022-09-06

申请号：US16849630

申请日：2020-04-15

Applicant: Tokyo Electron Limited

Inventor： Lars Liebmann ,  Jeffrey Smith ,  Anton deVilliers ,  Daniel Chanemougame

IPC: H01L27/092 ,  H01L29/08 ,  H01L23/535 ,  H01L23/528 ,  H03K19/21

Abstract: A 3D IC includes a substrate having a substrate surface, a first stack of semiconductor devices stacked along a thickness direction of the substrate, and a second stack of semiconductor devices stacked along the thickness direction of the substrate and provided adjacent to the first stack in a direction along the substrate surface. Each semiconductor device of the first and second stack includes a gate and a pair of source-drain regions provided on opposite sides of the respective gate, and each gate of the first and second stack is a split gate. A gate contact is physically connected to a first split gate of a first one of the semiconductor devices. The gate contact forms at least part of a local interconnect structure that electrically connects the first semiconductor device to a second semiconductor device in the 3D IC.

公开(公告)号：US11322401B2

公开(公告)日：2022-05-03

申请号：US17034930

申请日：2020-09-28

Applicant: Tokyo Electron Limited

Inventor： Jeffrey Smith ,  Lars Liebmann ,  Daniel Chanemougame ,  Hiroki Niimi ,  Kandabara Tapily ,  Subhadeep Kal ,  Jodi Grzeskowiak ,  Anton Devilliers

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming BPR structures filled with a replacement BPR material, first S/D structures, first replacement silicide layers, and a pre-metallization dielectric that covers the first replacement silicide layers and the first S/D structures. The method also includes forming first interconnect openings in the pre-metallization dielectric and first replacement interconnect layers in the first interconnect openings. The first replacement interconnect layers are connected to the first replacement silicide layers. A thermal process is executed. The method further includes replacing, from a first side of the first wafer, a first group of the first replacement interconnect layers, a first group of the first replacement silicide layers, and the replacement BPR material, and replacing, from a second side of the first wafer, a second group of the first replacement interconnect layers, and a second group of the first replacement silicide layers.

公开(公告)号：US20220068921A1

公开(公告)日：2022-03-03

申请号：US17222495

申请日：2021-04-05

Applicant: Tokyo Electron Limited

Inventor： Daniel Chanemougame ,  Lars Liebmann ,  Jeffrey Smith

IPC: H01L27/092 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238

Abstract: A first transistor tier is formed over a substrate, positioned in a first tier of the semiconductor device and includes bottom transistors extending along a horizontal direction parallel to the substrate. A first segment of a first conductive plane is formed in the first tier and adjacent to a first side of the first transistor tier, spans a height of the first transistor tier, and is connected to the first transistor tier. A second transistor tier is formed over the first transistor tier, positioned in a second tier of the semiconductor device and includes top transistors extending along the horizontal direction. A second segment of the first conductive plane is formed in the second tier and adjacent to a first side of the second transistor tier, positioned over and connected to the first segment of the first conductive plane, and spans a height of the second transistor tier.

公开(公告)号：US11264274B2

公开(公告)日：2022-03-01

申请号：US17010491

申请日：2020-09-02

Applicant: Tokyo Electron Limited

Inventor： Jeffrey Smith ,  Hiroaki Niimi ,  Jodi Grzeskowiak ,  Daniel Chanemougame ,  Lars Liebmann ,  Kandabara Tapily ,  Subhadeep Kal ,  Anton J. deVilliers

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092

Abstract: A first source/drain (S/D) structure of a first transistor is formed on a substrate and positioned at a first end of a first channel structure of the first transistor. A first substitute silicide layer is deposited on a surface of the first S/D structure and made of a first dielectric. A second dielectric is formed to cover the first substitute silicide layer and the first S/D structure. A first interconnect opening is formed subsequently in the second dielectric to uncover the first substitute silicide layer. The first interconnect opening is filled with a first substitute interconnect layer, where the first substitute interconnect layer is made of a third dielectric. Further, a thermal processing of the substrate is executed. The first substitute interconnect layer and the first substitute silicide layer are removed. A first silicide layer is formed on the surfaces of the first S/D structure.

公开(公告)号：US20210319165A1

公开(公告)日：2021-10-14

申请号：US17219539

申请日：2021-03-31

Applicant: Tokyo Electron Limited

Inventor： Lars Liebmann

IPC: G06F30/392 ,  G03F1/70

Abstract: In an embodiment, a method includes: receiving data representative of an electrical circuit including an arrangement of devices, inputs, outputs, and power sources; determining a minimum number of segments based on the received data; grouping the devices into N segments based on common features shared between two or more of the devices, where N is equal to the minimum number of segments; and generating discrete portions of the grouped devices to form a physical layout representative of a physical manifestation of the electrical circuit, such that when the discrete portions are integrated together they form a physical manifestation of the electrical circuit.

公开(公告)号：US20210202500A1

公开(公告)日：2021-07-01

申请号：US17139303

申请日：2020-12-31

Applicant: Tokyo Electron Limited

Inventor： Daniel CHANEMOUGAME ,  Lars Liebmann ,  Jeffrey Smith

IPC: H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A static random access memory (SRAM) structure is provided. The structure includes a plurality of SRAM bit cells on a substrate. Each SRAM bit cell includes at least six transistors including at least two NMOS transistors and at least two PMOS transistors. Each of the six transistors is being lateral gate-all-around transistors in that gates wraps all around a cross section of channels of the at least six transistors. The at least six transistors positioned in three decks in which a third deck is positioned vertically above a second deck, and the second deck is positioned vertically above a first deck relative to a working surface of the substrate. A first inverter is formed using a first transistor positioned in the first deck and a second transistor positioned in the second deck. A second inverter is formed using a third transistor positioned in the first deck and a fourth transistor positioned in the second deck. A pass gate is located in the third deck.

公开(公告)号：US20210118799A1

公开(公告)日：2021-04-22

申请号：US16660448

申请日：2019-10-22

Applicant: Tokyo Electron Limited

Inventor： Lars Liebmann ,  Jeffrey Smith ,  Anton deVilliers

IPC: H01L23/528 ,  H01L27/092 ,  H01L25/07 ,  H01L21/768

Abstract: Aspects of the disclosure provide a semiconductor apparatus including a plurality of structures. A first one of the structures comprises a first stack of transistors that includes a first transistor formed on a substrate and a second transistor stacked on the first transistor along a Z direction substantially perpendicular to a substrate plane of the semiconductor apparatus. The first one of the structures further includes local interconnect structures. The first transistor is sandwiched between two of the local interconnect structures. The first one of the structures further includes vertical conductive structures substantially parallel to the Z direction. The vertical conductive structures are configured to provide at least power supplies for the first one of the structures by electrically coupling with the local interconnect structures. A height of one of the vertical conductive structures along the Z direction is at least a height of the first one of the structures.

公开(公告)号：US20200373330A1

公开(公告)日：2020-11-26

申请号：US16716901

申请日：2019-12-17

Applicant: Tokyo Electron Limited

Inventor： Lars Liebmann ,  Jeffrey Smith ,  Anton J. deVilliers ,  Kandabara Tapily

IPC: H01L27/118 ,  H01L23/522 ,  H01L27/02 ,  H01L21/768 ,  H01L27/105

Abstract: A semiconductor device includes a coaxial contact that has conductive layers extending from local interconnects and being coupled to metal layers. The local interconnects are stacked over a substrate and extend laterally along a top surface of the substrate. The metal layers are stacked over the local interconnects and extend laterally along the top surface of the substrate. The conductive layers are close-shaped and concentrically arranged, where each of the local interconnects is coupled to a corresponding conductive layer, and each of the conductive layers is coupled to a corresponding metal layer. The semiconductor device also includes insulating layers that are close-shaped, concentrically arranged, and positioned alternately with respect to the conductive layers so that the conductive layers are spaced apart from one another by the insulating layers.