公开(公告)号：US09390796B2

公开(公告)日：2016-07-12

申请号：US14790430

申请日：2015-07-02

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Chang Hua Siau ,  Bruce Lynn Bateman

IPC: G11C5/06 ,  G11C13/00 ,  G11C5/08 ,  G11C7/00 ,  G11C7/18 ,  G11C7/04 ,  G11C7/12 ,  G11C16/24

CPC classification number: G11C5/06 ,  G11C5/08 ,  G11C7/00 ,  G11C7/04 ,  G11C7/12 ,  G11C7/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/24 ,  G11C2213/71

Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

公开(公告)号：US20150302923A1

公开(公告)日：2015-10-22

申请号：US14790430

申请日：2015-07-02

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Chang Hua Siau ,  Bruce Lynn Bateman

IPC: G11C13/00

CPC classification number: G11C5/06 ,  G11C5/08 ,  G11C7/00 ,  G11C7/04 ,  G11C7/12 ,  G11C7/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/24 ,  G11C2213/71

Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

Abstract translation: 存储器阵列包括字线，本地位线，双端存储器元件，全局位线以及局部到全局位线传递门​​和增益级。 存储元件形成在字线和本地位线之间。 每个本地位线通过相关联的局部到全局位线传递门​​选择性地耦合到相关联的全局位线。 在选择本地位线的存储元件被读取的读取操作期间，局部到全局增益级被配置为将本地位线上的信号放大到相关联的全局位线上或沿相关联的全局位线 。 在一个实施例中放大的信号取决于所选择的存储器元件的电阻状态，被用于快速地确定由所选择的存储器元件存储的存储器状态。 全局位线和/或选定的局部位线可被偏置以补偿过程电压温度（PVT）变化。

公开(公告)号：US09029827B2

公开(公告)日：2015-05-12

申请号：US14062609

申请日：2013-10-24

Applicant: Unity Semiconductor Corporation

Inventor： Lidia Vereen ,  Bruce Lynn Bateman ,  Louis Parrillo ,  Elizabeth Friend ,  David Eggleston

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/145 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1666 ,  H01L45/1683

Abstract: In an example, a single damascene structure is formed by, for example, providing a dielectric layer, forming a void in the dielectric layer, and forming a portion of a first two-terminal resistive memory cell and a portion of a second two-terminal resistive memory cell within the void. The portions of the two-terminal resistive memory cells may be vertically stacked within the void.

Abstract translation: 在一个示例中，通过例如提供电介质层，在电介质层中形成空隙，以及形成第一两端电阻存储单元的一部分和第二两端的一部分，形成单个镶嵌结构 电阻记忆体在空隙内。 两端电阻式存储单元的部分可以垂直地堆叠在空隙内。

公开(公告)号：US20150097155A1

公开(公告)日：2015-04-09

申请号：US14568802

申请日：2014-12-12

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Bruce Lynn Bateman

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/249 ,  H01L27/2418 ,  H01L27/2454 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

Abstract: An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

Abstract translation: 超高密度垂直交叉点阵列包括多个水平线层，水平线与以行和列排列的多条垂直线交错。 垂直线与水平线交错，使得一行垂直线位于每条水平线层中每条连续的一对水平线之间。 每个垂直线包括由单层或多层记忆膜包围的中心导体。 因此，当与水平线交错时，两端存储单元一体地形成在每条垂直线的中心导体和每个交叉水平线之间。 通过配置垂直和水平线，使得一行垂直线位于每条连续的一对水平线之间，可以实现仅仅2F2的单位存储单元占用空间。