公开(公告)号：US20090127679A1

公开(公告)日：2009-05-21

申请号：US11984772

申请日：2007-11-21

Applicant: Wen-Jeng Fan ,  Cheng-Pin Chen

Inventor： Wen-Jeng Fan ,  Cheng-Pin Chen

IPC: H01L23/495

CPC classification number: H01L23/4951 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: A POP (Package-On-Package) semiconductor device with encapsulating protection of soldered joints between the external leads, primarily comprises a plurality of stacked semiconductor packages and dielectric coating. Each semiconductor package includes at least a chip, a plurality of external leads of leadframe, and an encapsulant where the external leads are exposed and extended from a plurality of sides of the encapsulant. Terminals of a plurality external leads of a top semiconductor package are soldered to the soldered regions of the corresponding external leads of a bottom semiconductor package. The dielectric coating is disposed along the sides of the encapsulant of the bottom semiconductor package to connect the soldered points between the external leads and to partially or completely encapsulate the soldering materials so that the stresses between the soldered joints can be dispersed and no electrical shorts happen.

Abstract translation: 具有在外部引线之间的焊接接头的封装保护的POP（封装封装）半导体器件主要包括多个堆叠的半导体封装和电介质涂层。 每个半导体封装包括至少一个芯片，多个引线框的外部引线以及外部引线从密封剂的多个侧面露出和延伸的密封剂。 顶部半导体封装的多个外部引线的端子焊接到底部半导体封装的相应外部引线的焊接区域。 电介质涂层沿着底部半导体封装的密封剂的侧面设置，以将焊接点连接到外部引线之间并且部分或完全地封装焊接材料，使得焊接接头之间的应力可以分散并且不发生电短路 。

公开(公告)号：US20090091027A1

公开(公告)日：2009-04-09

申请号：US11905947

申请日：2007-10-05

Applicant: Wen-Jeng Fan

Inventor： Wen-Jeng Fan

IPC: H01L23/48

CPC classification number: H05K3/3436 ,  H01L24/16 ,  H01L24/32 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/732 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H05K2201/0367 ,  H05K2201/09845 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package with crack-restraining ring surfaces is revealed, primarily comprising a chip carrier, a chip disposed on the chip carrier, and a plurality of belfry-like bumps. The belfry-like bumps are disposed on a plurality of corresponding conductive pads on the bottom surface of the chip carrier as external terminals. Each belfry-like bump has at least a crack-restraining ring surface parallel to the conductive pads and between the top of the belfry-like bump and the conductive pad to prevent the spreading of the soldering cracks and to enhance the soldering strengths at the micro contacts to achieve higher package reliability.

Abstract translation: 揭示了具有裂纹抑制环表面的半导体封装，主要包括芯片载体，设置在芯片载体上的芯片和多个钟形凸起。 钟形凸起布置在作为外部端子的芯片载体的底表面上的多个对应的导电焊盘上。 每个钟形凸起至少具有平行于导电焊盘并且在钟形凸起的顶部和导电焊盘之间的裂纹抑制环表面，以防止焊接裂纹的扩展并且增强微型焊接强度 联系人实现更高的封装可靠性。

公开(公告)号：US20090091026A1

公开(公告)日：2009-04-09

申请号：US11905946

申请日：2007-10-05

Applicant: Wen-Jeng Fan

Inventor： Wen-Jeng Fan

IPC: H01L23/49

CPC classification number: H05K3/3436 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  H05K2201/0367 ,  H05K2201/0373 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A stackable semiconductor package is revealed, primarily comprising a chip carrier, a chip, and a plurality of bottom bump sets. The chip carrier has a plurality of stacking pads disposed on the top surface and a plurality of bump pads on the bottom surface. The chip is disposed on and electrically connected to the chip carrier. The bottom bump sets are disposed on the corresponding bump pads and each consists of a plurality of conductive pillars. Solder-filling gaps are formed between the adjacent conductive pillars for filling and holding solder paste so that the soldering area can be increase and the anchoring effect can be enhanced due to complicated the soldering interfaces to achieve higher soldering reliability and less cracks at the soldering interfaces.

Abstract translation: 揭示了可堆叠的半导体封装，主要包括芯片载体，芯片和多个底部凹凸组。 芯片载体具有设置在顶表面上的多个堆叠焊盘和底表面上的多个焊盘。 芯片设置在芯片载体上并电连接到芯片载体上。 底部凸块设置在相应的凸块上，每个由多个导电支柱组成。 在相邻的导电柱之间形成焊接填充间隙，用于填充和保持焊膏，从而可以增加焊接区域，并且由于焊接界面复杂，可以提高锚固效果，从而实现更高的焊接可靠性和较少的焊接界面处的裂纹 。

公开(公告)号：US20080169551A1

公开(公告)日：2008-07-17

申请号：US11653422

申请日：2007-01-16

Applicant: Wen-Jeng Fan ,  Li-Chih Fang

Inventor： Wen-Jeng Fan ,  Li-Chih Fang

IPC: H01L23/13

CPC classification number: H01L23/13 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An IC package with a near-substrate-scale die-attaching layer includes a substrate, a near-substrate-scale die-attaching layer, a chip, a plurality of bonding wires, an encapsulant, and a plurality of solder balls. A plurality of ball pads are formed on the bottom surface of the substrate for solder ball placement. The near-substrate-scale die-attaching layer is formed on the top surface of the substrate covering most of the top surface above the ball pads without extending to the edges of the top surface. The active surface of the chip is attached to a first portion of the near-substrate-scale die-attaching layer and is electrically connected to the substrate by the bonding wires. The encapsulant is formed above the top surface of the substrate to cover a second portion of the near-substrate-scale die-attaching layer extending between the substrate and the encapsulant. Therefore, without adding extra components, the intense thermal stresses imposed on some specific solder balls at the corners of the bottom surface of the substrate or under the edges of the chip will be reduced. During on-board TCT, the solder balls will not easily be broken so that the reliability of IC package is enhanced. Moreover, the near-substrate-scale die-attaching layer is completely encapsulated by the encapsulant 250 to have a better resistance to moisture.

Abstract translation: 具有近基板尺寸的芯片安装层的IC封装包括基板，近基板尺寸的芯片安装层，芯片，多个接合线，密封剂和多个焊球。 在用于焊球放置的基板的底面上形成有多个球垫。 接近基板的模具附接层形成在衬底的顶表面上，该顶表面覆盖球垫上方的大部分顶表面，而不延伸到顶表面的边缘。 芯片的有源表面附着在近基板尺寸的芯片安装层的第一部分上，并通过接合线与基板电连接。 密封剂形成在衬底的顶表面之上，以覆盖在衬底和密封剂之间延伸的接近衬底的管芯附着层的第二部分。 因此，在不增加额外的部件的情况下，施加在基板底面的拐角处或芯片边缘下方的一些特定焊球的强烈的热应力将会降低。 在板载TCT期间，焊球不容易断裂，从而提高了IC封装的可靠性。 此外，近基板尺寸的管芯附着层被密封剂250完全包封以具有更好的耐湿性。

公开(公告)号：US20080164610A1

公开(公告)日：2008-07-10

申请号：US11651610

申请日：2007-01-10

Applicant: Wen-Jeng Fan

Inventor： Wen-Jeng Fan

IPC: H01L23/00

CPC classification number: H05K1/111 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K2201/10734 ,  H05K2201/2072 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A substrate improving immobilization of ball pads for BGA packages mainly comprises a substrate core, a plurality of ball pads and a solder resist layer. Each of the ball pads has a metal pad and at least a metal nail. The metal pads are adhered on a surface of the substrate core and the metal nails are embedded into but not penetrate the substrate core. The solder resist layer is formed over the substrate core and exposes the metal pads. By utilizing the shapes of the ball pads to increase bonding area between the ball pads and the substrate core, a separation or crack occurring at the interface between the metal pads and the substrate core can be substantially avoided.

Abstract translation: 提高BGA封装的球垫的固定的基板主要包括基底芯，多个球垫和阻焊层。 每个球垫具有金属垫和至少一金属钉。 金属焊盘粘附在基板芯的表面上，并且金属钉被嵌入而不穿透基板芯。 阻焊层形成在衬底芯上并暴露金属焊盘。 通过利用球垫的形状来增加球垫和衬底芯之间的结合面积，可以基本上避免在金属垫和衬底芯之间的界面处发生的分离或裂纹。

公开(公告)号：US20080116574A1

公开(公告)日：2008-05-22

申请号：US11600916

申请日：2006-11-17

Applicant: Wen-Jeng Fan

Inventor： Wen-Jeng Fan

IPC: H01L23/48

CPC classification number: H01L23/49816 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A BGA package with encapsulation on substrate bottom comprises a chip, a substrate, a molding compound and a plurality of solder balls. The substrate has a SMT surface placing a plurality of ball pads. The molding compound encapsulates a solder resist layer on the SMT surface of the substrate and has a plurality of through holes exposing the ball pads respectively. The hole diameter of the through holes is greater than that of the openings of the solder resist layer on the substrate to allow the solder balls not to contact the molding compound. The solder balls are disposed in the through holes and are bonded to the exposed ball pads of the substrate thereby enhancing moisture resistance of BGA products and preventing the solder balls from falling because of contact stress of the molding compound.

Abstract translation: 在衬底底部封装的BGA封装包括芯片，衬底，模塑料和多个焊球。 衬底具有放置多个球垫的SMT表面。 模塑料在衬底的SMT表面上封装有阻焊层，并且具有多个通孔，分别暴露出焊盘。 通孔的孔径大于衬底上的阻焊层的开口的直径，以允许焊球不接触模塑料。 焊球设置在通孔中并与衬底的暴露的焊盘接合，从而增强了BGA产品的耐湿性，并防止由于模塑料的接触应力引起的焊球落下。

公开(公告)号：US20080099890A1

公开(公告)日：2008-05-01

申请号：US11589155

申请日：2006-10-30

Applicant: Cheng-Pin Chen ,  Wen-Jeng Fan ,  Li-chih Fang

Inventor： Cheng-Pin Chen ,  Wen-Jeng Fan ,  Li-chih Fang

IPC: H01L23/495

CPC classification number: H01L23/3128 ,  H01L23/49816 ,  H01L24/97 ,  H01L25/0655 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/18301 ,  H01L2924/00

Abstract: A ball grid array package structure includes: a substrate having at least one chip bearing area on its upper surface and a plurality of electrical-connecting points on its lower surface; a plurality of chips are arranged on the chip bearing area and electrically connected with those electrical-connecting points; a plurality of through holes penetrating the substrate at the edge of chip bearing area; an encapsulant used to cover those chip and filling those through holes to form a strengthened bump surrounding the chip bearing area on the lower surface of the substrate; and a plurality of conductive balls are respectively arranged on those electrical-connecting points. The present invention utilizes the strengthened bump on the bottom of the substrate to enhance the structure strength of the substrate so as to avoid the warpage of the substrate caused from the stress due to the temperature variation during the package process to affect the following processes.

Abstract translation: 球栅阵列封装结构包括：在其上表面上具有至少一个芯片支承区域的基板和其下表面上的多个电连接点; 多个芯片布置在芯片支承区域上并与那些电连接点电连接; 在芯片承载区域的边缘处穿过基板的多个通孔; 用于覆盖那些芯片并填充这些芯片的密封剂，以形成围绕衬底的下表面上的芯片支承区域的加强凸块; 并且在这些电连接点上分别布置有多个导电球。 本发明利用基板底部的加强凸块来增强基板的结构强度，以避免由于包装过程中的温度变化而引起的应力引起的基板翘曲影响以下工艺。

公开(公告)号：US08299587B2

公开(公告)日：2012-10-30

申请号：US12764596

申请日：2010-04-21

Applicant: Wen-Jeng Fan

Inventor： Wen-Jeng Fan

IPC: H01L23/495

CPC classification number: H01L23/49575 ,  H01L23/4951 ,  H01L23/49513 ,  H01L23/49551 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A lead frame package structure for side-by-side disposed chips including a lead frame, at least two chips, and a package material. The lead frame includes a plurality of inner leads; a plurality of outer leads; and at least two chip carrying areas having different horizontal levels. The chips are of different sizes and are respectively disposed on the chip carrying areas. The package material encapsulate the inner leads, the chip carrying areas and the chips, wherein the outer leads exposed out of the package material extend from the inner leads and have different horizontal levels.

Abstract translation: 一种用于并排设置的芯片的引线框架封装结构，包括引线框架，至少两个芯片和封装材料。 引线框架包括多个内引线; 多个外引线; 以及具有不同水平高度的至少两个芯片承载区域。 芯片尺寸不同，分别设置在芯片承载区域上。 封装材料封装内部引线，芯片承载区域和芯片，其中从封装材料暴露的外部引线从内部引线延伸并且具有不同的水平水平。

公开(公告)号：US07919851B2

公开(公告)日：2011-04-05

申请号：US12133841

申请日：2008-06-05

Applicant: Wen-Jeng Fan

Inventor： Wen-Jeng Fan

IPC: H01L23/12

CPC classification number: H05K3/3452 ,  H01L23/13 ,  H01L23/498 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K2201/068 ,  H05K2203/1572 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A laminated substrate and the semiconductor package utilizing the substrate are revealed. The laminated substrate primarily comprises a core layer, a first metal layer and a first solder mask disposed on the bottom surface of the core layer, and a second metal layer and a second solder mask disposed on the top surface of the core layer. The two solder masks have different CTEs to compensate potential substrate warpage caused by thermal stresses. Therefore, the manufacturing cost of the substrate can be reduced without adding extra stiffeners nor changing thicknesses of semiconductor packages to suppress substrate warpage during packaging processes. Especially, a die-attaching layer partially covers the second solder mask by printing and is planar after pre-curing for zero-gap die-attaching.

Abstract translation: 揭示层叠基板和利用基板的半导体封装。 层叠基板主要包括芯层，第一金属层和设置在芯层的底表面上的第一焊料掩模，以及设置在芯层的顶表面上的第二金属层和第二焊料掩模。 两个焊接掩模具有不同的CTE以补偿由热应力引起的潜在的基板翘曲。 因此，可以减少基板的制造成本，而不增加额外的加强件，也可以改变半导体封装的厚度，以抑制封装工艺期间的基板翘曲。 特别地，芯片安装层通过印刷部分地覆盖第二焊料掩模，并且在预固化之后是平面的，用于零间隙管芯附着。

公开(公告)号：US07821112B2

公开(公告)日：2010-10-26

申请号：US12044990

申请日：2008-03-09

Applicant: Wen-Jeng Fan ,  Yu-Mei Hsu

Inventor： Wen-Jeng Fan ,  Yu-Mei Hsu

IPC: H01L23/495

CPC classification number: H01L23/49503 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/85411 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor device having linear zigzag(s) for wire bonding is revealed, primarily comprising a chip, a plurality of leads made of a lead frame and a plurality of bonding wires electrically connecting the chip and the leads. At least one of the leads has a linear zigzag including a first finger and a second finger connected each other in a zigzag form. One end of one of the bonding wire is bonded to a bonding pad on the chip and the other end is selectively bonded to either the first finger or the second finger but not both in a manner that the wire-bonding direction of the bonding wire is parallel to or in a sharp angle with the direction of the connected fingers for easy wire bonding processes. Therefore, the semiconductor device can assemble chips with diverse dimensions or with diverse bonding pads layouts by flexible wire-bonding angles at linear zigzag to avoid electrical short between the adjacent leads.

Abstract translation: 揭示了具有用于引线键合的线性锯齿形的半导体器件，主要包括芯片，由引线框架制成的多个引线和电连接芯片和引线的多个接合线。 引线中的至少一个具有包括以锯齿形形式彼此连接的第一手指和第二手指的线性之字形。 接合线中的一个的一端被接合到芯片上的接合焊盘，另一端选择性地接合到第一指状物或第二指状物上，但不是以使得接合线的引线键合方向为 与连接的手指的方向平行或成锐角，以便于引线接合过程。 因此，半导体器件可以通过线性锯齿形的柔性引线接合角度来组装具有不同尺寸的芯片或具有不同的焊盘布局，以避免相邻引线之间的电短路。