公开(公告)号：US20210057442A1

公开(公告)日：2021-02-25

申请号：US16684844

申请日：2019-11-15

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zhong ZHANG ,  Wenxi ZHOU ,  Zhiliang XIA

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L29/66

Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes gate layers and insulating layers that are stacked alternatingly along a direction perpendicular to a substrate of the semiconductor device and form a stack upon the substrate. The semiconductor device includes an array of channel structures that are formed in an array region of the stack. Further, the semiconductor device includes a first staircase formed of a first section of the stack in a connection region upon the substrate, and a second staircase formed of a second section of the stack in the connection region upon the substrate. In addition, the semiconductor device includes a dummy staircase formed of the first section of the stack and disposed between the first staircase and the second staircase in the connection region.

公开(公告)号：US20200335167A1

公开(公告)日：2020-10-22

申请号：US16915606

申请日：2020-06-29

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zongliang HUO ,  Li Hong XIAO ,  Zhiliang XIA

IPC: G11C16/08 ,  G11C16/04 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/792

Abstract: Embodiments of three-dimensional memory device architectures and fabrication methods therefor are disclosed. In an example, the memory device includes a substrate and one or more peripheral devices on the substrate. The memory device also includes one or more interconnect layers and a semiconductor layer disposed over the one or more interconnect layers. A layer stack having alternating conductor and insulator layers is disposed above the semiconductor layer. A plurality of structures extend vertically through the layer stack. A first set of conductive lines are electrically coupled with a first set of the plurality of structures and a second set of conductive lines are electrically coupled with a second set of the plurality of structures different from the first set. The first and second sets of conductive lines are vertically distanced from opposite ends of the plurality of structures.

公开(公告)号：US20200321215A1

公开(公告)日：2020-10-08

申请号：US16909510

申请日：2020-06-23

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Lu Ming FAN ,  Zi Qun HUA ,  Bi Feng LI ,  Qingchen CAO ,  Yaobin FENG ,  Zhiliang XIA ,  Zongliang HUO

IPC: H01L21/033 ,  H01L21/768

Abstract: A method for forming a semiconductor structure including forming a plurality of mandrel lines on a first dielectric layer and forming one or more groups of discontinuous mandrel line pairs with a first mask. The method further includes disposing a second dielectric layer, and forming dielectric spacers on sidewalls of the mandrel lines and the discontinuous mandrel line pairs. The method further includes removing the mandrel lines and the discontinuous mandrel line pairs to form spacer masks, forming one or more groups of blocked regions using a second mask, and forming openings extended through the first dielectric layer with a conjunction of the spacer masks and the second mask. The method also includes removing the spacer masks and the second mask, disposing an objective material in the openings, and forming objective lines with top surfaces coplanar with the top surfaces of the first dielectric layer.

公开(公告)号：US20200176058A1

公开(公告)日：2020-06-04

申请号：US16713401

申请日：2019-12-13

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zongliang HUO ,  Jun LIU ,  Zhiliang XIA ,  Li Hong XIAO

IPC: G11C16/08 ,  H01L29/792 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11556 ,  G11C16/04

Abstract: A memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first substrate and one or more peripheral devices on the first substrate. The second semiconductor structure includes a first set of conductive lines electrically coupled with a first set of a plurality of vertical structures and a second set of conductive lines electrically coupled with a second set of the plurality of vertical structures different from the first set of the plurality of vertical structures. The first set of conductive lines are vertically distanced from one end of the plurality of vertical structures and the second set of conductive lines are vertically distanced from an opposite end of the plurality of vertical structures.

公开(公告)号：US20250120090A1

公开(公告)日：2025-04-10

申请号：US18987040

申请日：2024-12-19

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun CHEN ,  Zhiliang XIA ,  Li Hong XIAO

IPC: H10B43/40 ,  H10B43/27 ,  H10B43/35

Abstract: Embodiments of 3D memory devices and fabricating methods thereof are disclosed. The method comprises forming an array device semiconductor structure comprising an alternating conductor/dielectric stack disposed on a semiconductor layer, and an array interconnect layer disposed on the alternating conductor/dielectric stack and including a first interconnect structure. The method further comprises a peripheral device disposed on a substrate, and a peripheral interconnect layer disposed on the peripheral device and including a second interconnect structure and a pad. The pad is electrically connected with the peripheral device through the second interconnect structure. The method further comprises bonding the array interconnect layer to the peripheral interconnect layer, such that the first interconnect structure is joined with the second interconnect structure. The method further comprises forming a pad opening exposing a surface of the pad.

公开(公告)号：US20240397718A1

公开(公告)日：2024-11-28

申请号：US18789236

申请日：2024-07-30

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Zhong ZHANG ,  Zhongwang SUN ,  Wenxi ZHOU ,  Zhiliang XIA

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A semiconductor device includes a first bottom select gate (BSG) staircase, a first array region, a connection region, a second array region, and a second BSG staircase that are formed in a stack and disposed sequentially along a first direction of a substrate. The stack is formed of word line layers and insulating layers that are alternatingly disposed over the substrate. The first BSG staircase is formed in a first group of the word line layers, and the insulating layers and the second BSG staircase are formed in a second group of the word line layers and the insulating layers. The connection region includes a first top select gate (TSG) staircase positioned along the first array region, and a second TSG staircase positioned along the second array region. The first TSG staircase is formed in a third group of the word line layers, and the insulating layers and the second TSG staircase are formed in a fourth group of the word line layers and the insulating layers. The first TSG staircase and the second TSG staircase are positioned above the first BSG staircase and the second BSG staircase.

公开(公告)号：US20240339404A1

公开(公告)日：2024-10-10

申请号：US18739536

申请日：2024-06-11

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zhongwang SUN ,  Zhong ZHANG ,  Wenxi ZHOU ,  Zhiliang XIA

IPC: H01L23/528 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/535 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40 ,  H10B43/50

CPC classification number: H01L23/5283 ,  H01L21/311 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/535 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40 ,  H10B43/50

Abstract: In a method for fabricating a semiconductor device, an initial stack of sacrificial word line layers and insulating layers is formed over a substrate of the semiconductor device. The sacrificial word line layers and the insulating layers are disposed over the substrate alternately. A first staircase is formed in a first staircase region of a connection region of the initial stack. A second staircase is formed in a second staircase region of the connection region of the initial stack. The connection region of the initial stack includes a separation region between the first and second staircases, and the connection region is positioned between array regions of the initial stack at opposing sides of the initial stack.

公开(公告)号：US20240282376A1

公开(公告)日：2024-08-22

申请号：US18631706

申请日：2024-04-10

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： DongXue ZHAO ,  Tao YANG ,  Yuancheng YANG ,  Lei LIU ,  Di WANG ,  Kun ZHANG ,  Wenxi ZHOU ,  Zhiliang XIA ,  Zongliang HUO

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: A method for performing an erasing operation on a memory device is provided. The memory device includes a bottom select gate, a plate line above the bottom select gate, a word line above the plate line, a pillar extending through the bottom select gate, the plate line, and the word line, a source line under the pillar, a drain cap above the pillar, and a bit line formed above the drain cap. A first positive voltage bias is applied to the bottom select gate. A second positive voltage bias is applied to the plate line. The first positive voltage bias to the bottom select gate is reduced. A negative voltage bias is applied to the source line.

公开(公告)号：US20240274535A1

公开(公告)日：2024-08-15

申请号：US18644606

申请日：2024-04-24

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Di WANG ,  Wenxi ZHOU ,  Zhiliang XIA ,  Zhong ZHANG

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76825 ,  H01L21/76877 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: In an example of the present disclosure, a three-dimensional (3D) memory device includes a memory array structure and a staircase structure. The staircase structure includes a plurality of stairs extending along a first lateral direction. The plurality of stairs include a stair including a conductor portion on a top surface of the stair. The conduction portion is connected to the memory array structure. Widths of conductor portions are different in a second lateral direction perpendicular to the first lateral direction.

公开(公告)号：US20240215458A1

公开(公告)日：2024-06-27

申请号：US18089838

申请日：2022-12-28

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Yuxuan FANG ,  Shan LI ,  Dongxue ZHAO ,  Lei LIU ,  Zhiliang XIA

IPC: H10N50/10 ,  H01L23/528 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/10 ,  H01L23/5283 ,  H10B61/20 ,  H10N50/01

Abstract: A memory device includes a semiconductor layer and a stack structure over the semiconductor layer. The stack structure includes a cell array region and a staircase structure region. The cell array region includes multiple vertical levels of stacked transistor-magnetic tunnel junction (TMTJ) elements and a plurality of channel structures vertically extending through the stack structure. At least one channel structure includes a vertical core, a vertical magnetic reference layer, and a vertical tunnel barrier layer, which are shared by a set of magnetic tunnel junction (MTJ) elements associated with the at least one channel structure. The set of MTJ elements are located at different vertical levels of the stack structure.