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公开(公告)号：US09619288B2
公开(公告)日：2017-04-11
申请号：US15221936
申请日：2016-07-28
Applicant: SILICON GRAPHICS INTERNATIONAL CORP.
Inventor： Sanhita Sarkar , Raymon Morcos
CPC classification number: G06F9/5016 , G06F9/5027 , G06F9/5055
Abstract: A system for deploying big data software in a multi-instance node. The optimal CPU memory and core configuration for a single instance database is determined. After determining an optimal core-memory ratio for a single instance execution, the software is deployed in multi-instance mode on single machine by applying the optimal core-memory ratio for each of the instances. The multi-instance database may then be deployed and data may be loaded in parallel for the instances.
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公开(公告)号：US09547882B2
公开(公告)日：2017-01-17
申请号：US14537839
申请日：2014-11-10
Applicant: Silicon Graphics International Corp.
Inventor： Cheng Liao
CPC classification number: G06F9/544 , G06F9/4887 , G06F9/5016 , G06F9/5066 , G06F12/08 , G06F17/16 , G06F2212/2542 , G06T1/60
Abstract: Disclosed herein is a shared memory systems that use a combination of SBR and MRRR techniques to calculate eigenpairs for dense matrices having very large numbers of rows and columns. The disclosed system allows for the use of a highly scalable tridiagonal eigensolver. The disclosed system likewise allows for allocating a different number of threads to each of the different computational stages of the eigensolver.
Abstract translation: 这里公开了一种共享存储器系统，其使用SBR和MRRR技术的组合来计算具有非常大数量的行和列的密集矩阵的特征对。 所公开的系统允许使用高度可缩放的三角形固定器。 所公开的系统同样允许将不同数量的线程分配给固定器的不同计算阶段。
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公开(公告)号：US09461422B2
公开(公告)日：2016-10-04
申请号：US14529050
申请日：2014-10-30
Applicant: SILICON GRAPHICS INTERNATIONAL CORP.
Inventor： Peter Siltex Yuen
IPC: H01R24/60 , H01R24/64 , H01R13/502 , H01R13/66 , H01R13/6581 , H01R13/6599 , H01R12/50 , H01R24/68
CPC classification number: H01R24/60 , H01R13/502 , H01R13/6581 , H01R13/6599 , H01R13/6658 , H01R23/7073 , H01R24/64 , H01R24/68
Abstract: In an embodiment, a micro ethernet connector includes an outer housing that has a recessed front end and a back end. The micro ethernet connector further includes an inner housing that is disposed within the recessed front end of the outer housing. The inner housing has an exposed end. The exposed end includes a recessed channel. The volume of the recessed channel is substantially equal to the volume of a correspondingly shaped protruding printed circuit board of a male micro ethernet connector. A plurality of spring-biased connectors are disposed within the recessed channel of the inner housing.
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公开(公告)号：US09262799B2
公开(公告)日：2016-02-16
申请号：US14536477
申请日：2014-11-07
Applicant: Silicon Graphics International Corp.
Inventor： Cheng Liao
CPC classification number: G06F9/544 , G06F9/4887 , G06F9/5016 , G06F9/5066 , G06F12/08 , G06F17/16 , G06F2212/2542 , G06T1/60
Abstract: A method for computing eigenvectors and eigenvalues of a square matrix in a high performance computer involves dynamically reallocating the computer's computing cores for various phases of the computation process.
Abstract translation: 用于计算高性能计算机中的方阵的特征向量和特征值的方法涉及对计算过程的各个阶段动态地重新分配计算机的计算核心。
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公开(公告)号：US09237093B2
公开(公告)日：2016-01-12
申请号：US13830432
申请日：2013-03-14
Applicant: Silicon Graphics International Corp.
Inventor： Joseph George Tietz , Gregory Michael Thorson , Eric C. Fromm
IPC: H04L12/721 , H04L12/703 , H04L12/803 , H04L12/707
CPC classification number: H04L45/28 , H04L45/22 , H04L45/70 , H04L47/122
Abstract: An adaptive router anticipates possible future congestion and enables selection of an alternative route before the congestion occurs, thereby avoiding the congestion. The adaptive router may use a primary route until it predicts congestion will occur. The adaptive router measures packet traffic volume, such as flit volume, on a primary network interface to anticipate the congestion. The adaptive router maintains a trailing sum of the number of flits handled by the primary network interface over a trailing time period. If the sum exceeds a threshold value, the adaptive router assumes the route will become congested, and the adaptive router enables considering routing future packets, or at least the current packet, over possible secondary routes.
Abstract translation: 自适应路由器预测可能的未来拥塞，并且能够在拥塞发生之前选择替代路由，从而避免拥塞。 自适应路由器可以使用主路由，直到它预测将发生拥塞。 自适应路由器在主网络接口上测量数据包流量，如flit volume，以预测拥塞。 自适应路由器在拖尾时间段内保持由主网络接口处理的飞行数量的拖尾和。 如果总和超过阈值，则自适应路由器假定路由将变得拥塞，并且自适应路由器能够考虑在可能的次路由上路由将来的分组，或至少当前分组。
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Patent Agency Ranking
36.发明申请公开(公告)号：US20150278040A1
公开(公告)日：2015-10-01
申请号：US14224795
申请日：2014-03-25
Applicant: Silicon Graphics International Corp.
CPC classification number: G06F13/4022 , G06F11/2007 , G06F2201/81 , G06F2201/85 , H04L1/1848 , H04L1/20 , H04L1/22 , H04L2001/0096
Abstract: A system and method provide a communications link having a plurality of lanes, and an in-band, real-time physical layer protocol that keeps all lanes on-line, while failing lanes are removed, for continuous service during fail over operations. Lane status is monitored real-time at the physical layer receiver, where link error rate, per lane error performance, and other channel metrics are known. If a lane failure is established, a single round trip request/acknowledge protocol exchange with the remote port completes the fail over. If a failing lane meets an acceptable performance level, it remains on-line during the round trip exchange, resulting in uninterrupted link service. Lanes may be brought in or out of service to meet reliability, availability, and power consumption goals.
Abstract translation: 系统和方法提供具有多个通道的通信链路，以及带内实时物理层协议，其在故障切换操作期间连续服务，保持所有车道在线，同时消除故障车道。 在物理层接收机处实时监控通道状态，其中链路错误率，每通道错误性能和其他信道度量是已知的。 如果建立通道故障，则与远程端口的单一往返请求/确认协议交换完成故障切换。 如果失败的车道达到可接受的性能水平，则在往返交换期间保持在线，导致不间断的链路服务。 车道可能被带入或不服务，以满足可靠性，可用性和功耗目标。
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37.发明授权Independent removable computer rack power distribution system for high-density clustered computer system 有权用于高密度集群计算机系统的独立可移动计算机机架配电系统公开(公告)号：US09128682B2
公开(公告)日：2015-09-08
申请号：US13949920
申请日：2013-07-24
Applicant: Silicon Graphics International Corp.
Inventor： Steven J. Dean , Robert E. Mascia , Harvey J. Lunsman , Michael Kubisiak , David R. Collins , Timothy S. McCann
CPC classification number: G06F1/20 , G06F1/181 , G06F2200/201 , H05K7/20754 , H05K7/20827
Abstract: A high performance computing system includes one or more blade enclosures configured to hold a plurality of computing blades, a connection interface, coupled to the one or more blade enclosures, having one or more connectors and a shared power bus that distributes power to the one or more blade enclosures, and at least one power shelf removably coupled to the one or more connectors and configured to hold one or more power supplies. The system may further include the computing blades and the power supplies. The power shelf may include a power distribution board configured to connect the power supplies together on the shared power bus.
Abstract translation: 高性能计算系统包括被配置为保持多个计算刀片的一个或多个刀片外壳，耦合到所述一个或多个刀片外壳的连接接口，其具有一个或多个连接器以及将功率分配给所述一个或多个连接器的共享电源总线 更多的刀片外壳，以及至少一个电源框架，其可移除地联接到所述一个或多个连接器并且被配置为保持一个或多个电源。 该系统还可以包括计算刀片和电源。 电源架可以包括配电板，其配置成在共享电力总线上将电源连接在一起。
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38.发明授权High performance system that includes reconfigurable protocol tables within an ASIC wherein a first protocol block implements an inter-ASIC communications protocol and a second block implements an intra-ASIC function 有权包括ASIC内的可重配置协议表的高性能系统，其中第一协议块实现ASIC间通信协议，第二块实现ASIC内部功能公开(公告)号：US09122816B2
公开(公告)日：2015-09-01
申请号：US14542023
申请日：2014-11-14
Applicant: Silicon Graphics International Corp.
Inventor： Thomas Edward McGee
CPC classification number: G06F13/4282 , G06F13/385 , Y02D10/14 , Y02D10/151
Abstract: A high performance computing system is provided with an ASIC that communicates with another device in the system according to a protocol defined by the other device. The ASIC is coupled to a reconfigurable protocol table, in the form of a high speed content-addressable memory (“CAM”). The CAM includes instructions to control the execution of the protocol by the ASIC. The CAM may include instructions to control the ASIC in the event that unanticipated signals or other errors are encountered while executing the protocol. Internal ASIC state data may be routed to the CAM to permit the ASIC to generate a reasonable response to errors either in the design or fabrication of the ASIC or the device with which it is communicating.
Abstract translation: 高性能计算系统提供有ASIC，其根据由另一设备定义的协议与系统中的另一设备进行通信。 ASIC以高速内容可寻址存储器（“CAM”）的形式耦合到可重配置协议表。 CAM包括用于控制由ASIC执行协议的指令。 CAM可以包括在执行协议时遇到意外的信号或其他错误的情况下控制ASIC的指令。 内部ASIC状态数据可以路由到CAM，以允许ASIC在ASIC或其正在通信的设备的设计或制造中产生对错误的合理响应。
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39.发明申请公开(公告)号：US20150007087A1
公开(公告)日：2015-01-01
申请号：US13931806
申请日：2013-06-28
Applicant: Silicon Graphics International Corp.
Inventor： Marc David Hansen
IPC: G06F3/0481 , G06F3/0484 , G06F3/0488
CPC classification number: G06F3/04815 , G06F3/0484
Abstract: Data visualization that interactively rotates data about a particular axis or translates data in a particular plane based on input received outside the axis space. Data to be visualized is accessed by a data visualization application. The data may be structured or unstructured, filtered and analyzed. The accessed data may be displayed through an interface of the visualization application for a user. The coordinate system for displaying the data may also be displayed. A user may rotate data about a particular axis of the coordinate system or translate data in a particular plane by providing a continuous input within a graphics portion of an interface. The input may be associated with a virtual track ball.
Abstract translation: 数据可视化，以交互方式旋转关于特定轴的数据或基于在轴空间外部接收的输入来转换特定平面中的数据。 数据可视化应用程序访问要显示的数据。 数据可以是结构化的或非结构化的，过滤的和分析的。 访问的数据可以通过用户的可视化应用的界面来显示。 也可以显示用于显示数据的坐标系。 用户可以通过在接口的图形部分内提供连续输入来旋转关于坐标系的特定轴的数据或者在特定平面中翻译数据。 输入可以与虚拟轨迹球相关联。
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40.发明授权High performance system that includes reconfigurable protocol tables within an ASIC wherein a first protocol block implements an inter-ASIC communications protocol and a second block implements an intra-ASIC function 有权包括ASIC内的可重配置协议表的高性能系统，其中第一协议块实现ASIC间通信协议，第二块实现ASIC内部功能公开(公告)号：US08892805B2
公开(公告)日：2014-11-18
申请号：US13788281
申请日：2013-03-07
Applicant: Silicon Graphics International Corp.
Inventor： Thomas Edward McGee
IPC: G06F13/00
CPC classification number: G06F13/4282 , G06F13/385 , Y02D10/14 , Y02D10/151
Abstract: A high performance computing system is provided with an ASIC that communicates with another device in the system according to a protocol defined by the other device. The ASIC is coupled to a reconfigurable protocol table, in the form of a high speed content-addressable memory (“CAM”). The CAM includes instructions to control the execution of the protocol by the ASIC. The CAM may include instructions to control the ASIC in the event that unanticipated signals or other errors are encountered while executing the protocol. Internal ASIC state data may be routed to the CAM to permit the ASIC to generate a reasonable response to errors either in the design or fabrication of the ASIC or the device with which it is communicating.
Abstract translation: 高性能计算系统提供有ASIC，其根据由另一设备定义的协议与系统中的另一设备进行通信。 ASIC以高速内容可寻址存储器（“CAM”）的形式耦合到可重配置协议表。 CAM包括用于控制由ASIC执行协议的指令。 CAM可以包括在执行协议时遇到意外的信号或其他错误的情况下控制ASIC的指令。 内部ASIC状态数据可以路由到CAM，以允许ASIC在ASIC或其正在通信的设备的设计或制造中产生对错误的合理响应。
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