公开(公告)号：US20100176489A1

公开(公告)日：2010-07-15

申请号：US12319650

申请日：2009-01-10

Applicant: Farrokh Ayazi ,  Mina Raieszadeh ,  Pezhman Monadgemi

Inventor： Farrokh Ayazi ,  Mina Raieszadeh ,  Pezhman Monadgemi

IPC: H01L29/93 ,  H01L21/3205 ,  H01L21/02

CPC classification number: H01L21/84 ,  B81B3/0086 ,  B81B2201/0221 ,  B81B2203/0118 ,  B81B2203/033 ,  B81C1/00619 ,  B81C2201/014 ,  H01L27/1203 ,  H01L28/60

Abstract: Disclosed are one-port and two-port microelectromechanical structures including variable capacitors, switches, and filter devices. High aspect-ratio micromachining is used to implement low-voltage, large value tunable and fixed capacitors, and the like. Tunable capacitors can move in the plane of the substrate by the application of DC voltages and achieve greater than 240 percent of tuning. Exemplary microelectromechanical apparatus comprises a single crystalline silicon substrate, and a conductive structure laterally separated from the single crystalline silicon substrate by first and second high aspect ratio gaps of different size, wherein at least one of the high aspect ratio gaps has an aspect ratio of at least 30:1, and is vertically anchored to the single crystalline silicon substrate by way of silicon nitride.

Abstract translation: 公开了包括可变电容器，开关和滤波器装置的单端口和双端口微机电结构。 高纵横比微加工用于实现低电压，大值可调谐和固定电容器等。 可调电容器可以通过施加直流电压在基板的平面内移动，并实现大于240％的调谐。 示例性微电子机械装置包括单晶硅衬底和通过不同尺寸的第一和第二高纵横比间隙从单晶硅衬底横向分离的导电结构，其中高纵横比间隙中的至少一个具有在 至少30:1，并且通过氮化硅垂直锚定到单晶硅衬底。

公开(公告)号：US07728252B2

公开(公告)日：2010-06-01

申请号：US11571600

申请日：2005-06-23

Applicant: Yasuhiro Morikawa ,  Toshio Hayashi ,  Koukou Suu

Inventor： Yasuhiro Morikawa ,  Toshio Hayashi ,  Koukou Suu

IPC: B23K10/00

CPC classification number: H01L21/30655 ,  B81C1/00595 ,  B81C2201/014 ,  H01J37/3255 ,  H01J2237/334

Abstract: An etching method and an etching system are adapted to produce a high etch selectivity for a mask, an excellent anisotropic profile and a large etching depth. An etching system according to the invention comprises a floating electrode arranged vis-à-vis a substrate electrode in a vacuum chamber and held in a floating state in terms of electric potential, a material arranged at the side of the floating electrode facing the substrate electrode to form an anti-etching film and a control unit for intermittently applying high frequency power to the floating electrode. An etching method according to the invention uses a material arranged at the side of the floating electrode opposite to the substrate electrode to form an anti-etching film as target and only rare gas as main gas and is adapted to repeat a step of forming a film on the substrate by sputtering by applying high frequency power to the floating electrode and a step of subsequently etching the substrate by suspending the application of high frequency power to the floating electrode and introducing etching gas into the vacuum chamber in a predetermined sequence (FIG. 1).

Abstract translation: 蚀刻方法和蚀刻系统适于产生掩模的高蚀刻选择性，优异的各向异性轮廓和大的蚀刻深度。 根据本发明的蚀刻系统包括相对于真空室中的基板电极布置并且在电位方面保持为浮置状态的浮动电极，布置在浮置电极的面对基板电极的一侧的材料 形成抗蚀刻膜和用于间歇地向浮动电极施加高频电力的控制单元。 根据本发明的蚀刻方法使用布置在与基板电极相对的浮动电极侧的材料以形成作为目标的抗蚀刻膜，并且仅将稀有气体作为主要气体，并且适于重复形成膜的步骤 通过向浮动电极施加高频电力而通过溅射在衬底上，以及通过将浮动电极悬浮施加高频电力并以预定顺序将蚀刻气体引入真空室中，随后蚀刻衬底的步骤（图1 ）。

公开(公告)号：US20090325335A1

公开(公告)日：2009-12-31

申请号：US12488854

申请日：2009-06-22

Applicant: François Perruchot ,  Bernard Diem ,  Vincent Larrey ,  Laurent Clavelier ,  Emmanuel Defay

Inventor： François Perruchot ,  Bernard Diem ,  Vincent Larrey ,  Laurent Clavelier ,  Emmanuel Defay

IPC: H01L21/302 ,  H01L21/02

CPC classification number: B81C1/00595 ,  B81B2201/0271 ,  B81C2201/0109 ,  B81C2201/014

Abstract: The invention relates to a method of making a component from a heterogeneous substrate comprising first and second portions in at least one monocrystalline material, and a sacrificial layer constituted by at least one stack of at least one layer of monocrystalline Si situated between two layers of monocrystalline SiGe, the stack being disposed between said first and second portions of monocrystalline material, wherein the method consists in etching said stack by making: e) at least one opening in the first and/or second portion and the first and/or second layer of SiGe so as to reach the layer of Si; and f) eliminating all or part of the layer of Si.

Abstract translation: 本发明涉及一种从包含至少一种单晶材料中的第一和第二部分的异质衬底制备组分的方法，以及由位于两层单晶之间的至少一层单晶硅的至少一个叠层构成的牺牲层 SiGe，堆叠设置在单晶材料的第一和第二部分之间，其中该方法包括通过以下步骤蚀刻所述堆叠：e）在第一和/或第二部分中的至少一个开口，以及第一和/ SiGe，以达到Si层; 和f）消除Si的全部或部分层。

公开(公告)号：US07411261B2

公开(公告)日：2008-08-12

申请号：US10773312

申请日：2004-02-09

Applicant: Eun-sung Lee ,  Chung-woo Kim ,  In-sang Song ,  Jong-seok Kim ,  Moon-chul Lee

Inventor： Eun-sung Lee ,  Chung-woo Kim ,  In-sang Song ,  Jong-seok Kim ,  Moon-chul Lee

IPC: H01L29/84

CPC classification number: B81B3/0078 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0307 ,  B81B2203/04 ,  B81C2201/0107 ,  B81C2201/014 ,  H01H59/0009

Abstract: A method for fabricating a MEMS device having a fixing part fixed to a substrate, a connecting part, a driving part, a driving electrode, and contact parts, includes patterning the driving electrode on the substrate; forming an insulation layer on the substrate; patterning the insulation layer and etching a fixing region and a contact region of the insulation layer; forming a metal layer over the substrate; planarizing the metal layer until the insulation layer is exposed; forming a sacrificial layer on the substrate; patterning the sacrificial layer to form an opening exposing a portion of the insulation layer and the metal layer in the fixing region; forming a MEMS structure layer on the sacrificial layer to partially fill the opening, thereby forming sidewalls therein; and selectively removing a portion of the sacrificial layer by etching so that a portion of the sacrificial layer remains in the fixing region.

Abstract translation: 一种用于制造具有固定到基板上的固定部件，连接部件，驱动部件，驱动电极和接触部件的MEMS器件的方法，包括在所述基板上图形化所述驱动电极; 在所述基板上形成绝缘层; 图案化绝缘层并蚀刻绝缘层的固定区域和接触区域; 在衬底上形成金属层; 平坦化金属层直到绝缘层露出; 在所述基板上形成牺牲层; 图案化牺牲层以形成露出固定区域中绝缘层和金属层的一部分的开口; 在所述牺牲层上形成MEMS结构层以部分地填充所述开口，从而在其中形成侧壁; 并且通过蚀刻选择性地去除牺牲层的一部分，使得牺牲层的一部分保留在固定区域中。

公开(公告)号：US07397097B2

公开(公告)日：2008-07-08

申请号：US10721524

申请日：2003-11-25

Applicant: Richard A. Blanchard ,  Joseph C. McAlexander

Inventor： Richard A. Blanchard ,  Joseph C. McAlexander

IPC: H01L23/48

CPC classification number: B81C1/00626 ,  B81B2201/0235 ,  B81B2203/0118 ,  B81B2203/033 ,  B81C2201/0109 ,  B81C2201/014

Abstract: A released beam structure fabricated in trench and manufacturing method thereof are provided herein. One embodiment of a released beam structure according to the present invention comprises a semiconductor substrate, a trench, a first conducting layer, and a beam. The trench extends into the semiconductor substrate and has walls. The first conducting layer is positioned over the walls of the trench at selected locations. The beam is positioned with the trench and is connected at a first portion thereof to the semiconductor substrate and movable at a second portion thereof. The second portion of the beam is spaced from the walls of the trench by a selected distance. Therefore, the second portion of the beam is free to move in a plane that is perpendicular or parallel to the surface of the substrate, and could be deflected to electrically contact with the walls of the trench in response to a predetermined acceleration force or a predetermined temperature variation applied on the beam structure. Other beam structures such as a beam held at both ends, or a beam held in the middle are also possible. Several beam structures at different angles can be fabricated simultaneously and mechanical etching stops are automatically formed to prevent unwanted overstress conditions when manufacturing several beam structures at the same time. Beam structures can also be manufactured in three orthogonal directions, providing information on acceleration in any direction.

Abstract translation: 本发明提供一种以沟槽制造的释放的束结构及其制造方法。 根据本发明的释放的光束结构的一个实施例包括半导体衬底，沟槽，第一导电层和光束。 沟槽延伸到半导体衬底中并具有壁。 第一导电层位于沟槽的选定位置的上方。 光束与沟槽定位并且在其第一部分处连接到半导体衬底并且可在其第二部分移动。 梁的第二部分与沟槽的壁间隔一定距离。 因此，梁的第二部分在垂直于或平行于衬底的表面的平面中自由移动，并且可以响应于预定的加速力或预定的加速力而被偏转以与沟槽的壁电接触 温度变化施加在梁结构上。 其他梁结构，例如保持在两端的梁或保持在中间的梁也是可能的。 可以同时制造不同角度的几个梁结构，并且自动形成机械蚀刻停止，以在同时制造几个梁结构时防止不想要的过应力条件。 梁结构也可以在三个正交方向上制造，提供关于任何方向上的加速度的信息。

公开(公告)号：US20080158645A1

公开(公告)日：2008-07-03

申请号：US11646059

申请日：2006-12-27

Applicant: Chih-Wei Chiang

Inventor： Chih-Wei Chiang

IPC: G02B26/02 ,  B05D5/06 ,  B05D5/12

CPC classification number: G02B26/001 ,  B81B2201/047 ,  B81C1/00801 ,  B81C2201/014 ,  B81C2201/112

Abstract: A microelectromechanical systems (MEMS) device utilizing an aluminum fluoride layer as an etch stop is disclosed. In one embodiment, a MEMS device includes a first electrode having a first surface; and a second electrode having a second surface facing the first surface and defining a gap therebetween. The second electrode is movable in the gap between a first position and a second position. At least one of the electrodes includes an aluminum fluoride layer facing the other of the electrodes. During fabrication of the MEMS device, a sacrificial layer is formed between the first and second electrodes and is released to define the gap. The aluminum fluoride layer serves as an etch stop to protect the first or second electrode during the release of the sacrificial layer.

Abstract translation: 公开了一种利用氟化铝层作为蚀刻阻挡层的微机电系统（MEMS）装置。 在一个实施例中，MEMS器件包括具有第一表面的第一电极; 以及第二电极，其具有面向所述第一表面的第二表面并且在其间限定间隙。 第二电极可以在第一位置和第二位置之间的间隙中移动。 至少一个电极包括面对另一个电极的氟化铝层。 在MEMS器件的制造期间，在第一和第二电极之间形成牺牲层并被释放以限定间隙。 氟化铝层用作蚀刻停止件，以在释放牺牲层期间保护第一或第二电极。

公开(公告)号：US07382515B2

公开(公告)日：2008-06-03

申请号：US11334990

申请日：2006-01-18

Applicant: Wonsuk Chung ,  Steve Zee ,  Teruo Sasagawa

Inventor： Wonsuk Chung ,  Steve Zee ,  Teruo Sasagawa

IPC: G02B26/00 ,  G02B26/08 ,  G02B27/00 ,  H01L21/302

CPC classification number: B81C1/00801 ,  B81B2201/047 ,  B81C2201/014 ,  G02B26/001 ,  Y10T428/31678

Abstract: The fabrication of a MEMS device such as an interferometric modulator is improved by employing an etch stop layer between a sacrificial layer and a an electrode. The etch stop may reduce undesirable over-etching of the sacrificial layer and the electrode. The etch stop layer may also serve as a barrier layer, buffer layer, and or template layer. The etch stop layer may include silicon-rich silicon nitride.

Abstract translation: 通过在牺牲层和电极之间采用蚀刻停止层来改善诸如干涉式调制器之类的MEMS器件的制造。 蚀刻停止可以减少对牺牲层和电极的不希望的过蚀刻。 蚀刻停止层也可以用作阻挡层，缓冲层和/或模板层。 蚀刻停止层可以包括富硅的氮化硅。

公开(公告)号：US07368313B2

公开(公告)日：2008-05-06

申请号：US11053115

申请日：2005-02-07

Applicant: Hubert Benzel ,  Gerhard Lammel

Inventor： Hubert Benzel ,  Gerhard Lammel

IPC: H01L29/04

CPC classification number: B81C1/00158 ,  B81B2201/0264 ,  B81C2201/0115 ,  B81C2201/014 ,  G01L9/0042 ,  G01L9/0054

Abstract: In a method for manufacturing a micromechanical semiconductor component, e.g., a pressure sensor, a locally limited, buried, and at least partially oxidized porous layer is produced in a semiconductor substrate. A cavity is subsequently produced in the semiconductor substrate from the back, directly underneath the porous first layer, using a trench etch process. The porous first layer is used as a stop layer for the trench. Thin diaphragms having a low thickness tolerance may thus be produced for differential pressure measurement.

Abstract translation: 在制造微机电半导体部件的方法中，例如压力传感器，在半导体衬底中产生局部限制的，掩埋的和至少部分氧化的多孔层。 随后，使用沟槽蚀刻工艺，在半导体衬底中从后部直接在多孔第一层下方产生空腔。 多孔第一层用作沟槽的停止层。 因此可以产生具有低厚度公差的薄膜，用于差压测量。

公开(公告)号：US20080032501A1

公开(公告)日：2008-02-07

申请号：US11459307

申请日：2006-07-21

Applicant: Jonathan L. Klein ,  Jorg Pilchowski

Inventor： Jonathan L. Klein ,  Jorg Pilchowski

IPC: H01L21/44

CPC classification number: B81C1/00579 ,  B81C2201/0107 ,  B81C2201/014

Abstract: Micro-electromechanical systems (MEMS) pre-fabrication products and methods for forming MEMS devices using silicon-on-metal (SOM) wafers. An embodiment of a method may include the steps of bonding a patterned SOM wafer to a cover wafer, thinning the handle layer of the SOM wafer, selectively removing the exposed metal layer, and either continuing with final metallization or cover bonding to the back of the active layer.

Abstract translation: 微机电系统（MEMS）预制产品和使用金属硅（SOM）晶片形成MEMS器件的方法。 方法的一个实施例可以包括以下步骤：将图案化的SOM晶片结合到覆盖晶片，使SOM晶片的手柄层变薄，选择性地去除暴露的金属层，并且继续进行最后的金属化或覆盖粘合到 活动层

公开(公告)号：US20070166844A1

公开(公告)日：2007-07-19

申请号：US11571600

申请日：2005-06-23

Applicant: Yasuhiro Morikawa ,  Toshio Hayashi ,  Koukou Suu

Inventor： Yasuhiro Morikawa ,  Toshio Hayashi ,  Koukou Suu

IPC: H01L21/00

CPC classification number: H01L21/30655 ,  B81C1/00595 ,  B81C2201/014 ,  H01J37/3255 ,  H01J2237/334

Abstract: An etching method and an etching system are adapted to produce a high etch selectivity for a mask, an excellent anisotropic profile and a large etching depth. An etching system according to the invention comprises a floating electrode arranged vis-à-vis a substrate electrode in a vacuum chamber and held in a floating state in terms of electric potential, a material arranged at the side of the floating electrode facing the substrate electrode to form an anti-etching film and a control unit for intermittently applying high frequency power to the floating electrode. An etching method according to the invention uses a material arranged at the side of the floating electrode opposite to the substrate electrode to form an anti-etching film as target and only rare gas as main gas and is adapted to repeat a step of forming a film on the substrate by sputtering by applying high frequency power to the floating electrode and a step of subsequently etching the substrate by suspending the application of high frequency power to the floating electrode and introducing etching gas into the vacuum chamber in a predetermined sequence (FIG. 1).

Abstract translation: 蚀刻方法和蚀刻系统适于产生掩模的高蚀刻选择性，优异的各向异性轮廓和大的蚀刻深度。 根据本发明的蚀刻系统包括相对于真空室中的基板电极布置并且在电位方面保持为浮置状态的浮动电极，布置在浮置电极的面向基板电极的一侧的材料 形成抗蚀刻膜和用于间歇地向浮动电极施加高频电力的控制单元。 根据本发明的蚀刻方法使用布置在与基板电极相对的浮动电极侧的材料以形成作为目标的抗蚀刻膜，并且仅将稀有气体作为主要气体，并且适于重复形成膜的步骤 通过向浮动电极施加高频电力而通过溅射在衬底上，并且通过将浮动电极悬浮施加高频电力并以预定顺序将蚀刻气体引入真空室中，随后蚀刻衬底的步骤（图1 ）。