公开(公告)号：US09792448B2

公开(公告)日：2017-10-17

申请号：US14494643

申请日：2014-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Kaplan ,  Thomas Roy Woller ,  Ronald Perez

IPC: G06F21/60 ,  G06F12/14 ,  G06F9/455

CPC classification number: G06F21/602 ,  G06F9/45558 ,  G06F12/1036 ,  G06F12/1408 ,  G06F21/53 ,  G06F2009/4557 ,  G06F2009/45583 ,  G06F2009/45587 ,  G06F2212/402

Abstract: A processor employs a hardware encryption module in the processor's memory access path to cryptographically isolate secure information. In some embodiments, the encryption module is located at a memory controller (e.g. northbridge) of the processor, and each memory access provided to the memory controller indicates whether the access is a secure memory access, indicating the data associated with the memory access is designated for cryptographic protection, or a non-secure memory access. For secure memory accesses, the encryption module performs encryption (for write accesses) or decryption (for read accesses) of the data associated with the memory access.

公开(公告)号：US20170277632A1

公开(公告)日：2017-09-28

申请号：US15505734

申请日：2014-10-30

Applicant: Hitachi, Ltd.

Inventor： Toshiomi MORIKI ,  Naoya HATTORI ,  Takayuki IMADA

IPC: G06F12/08 ,  G06F12/02 ,  G06F9/455

CPC classification number: G06F12/08 ,  G06F9/45558 ,  G06F9/5077 ,  G06F12/0223 ,  G06F12/1036 ,  G06F12/109 ,  G06F2009/45583 ,  G06F2212/1004 ,  G06F2212/1024 ,  G06F2212/151 ,  G06F2212/651 ,  G06F2212/652 ,  G06F2212/684

Abstract: A hypervisor that allocates the computer resource of a physical computer to one or more logical partitions allocates the computer resource to be allocated to the logical partitions to the logical partitions; generates, as address conversion information, the relationship between a guest physical address and a host physical address with respect to a memory of the computer resource; enables a first address conversion portion of a processor using the address conversion information; disables the first address conversion portion after the starting of a guest OS is completed; and causes an application to be executed.

公开(公告)号：US20170249181A1

公开(公告)日：2017-08-31

申请号：US15489398

申请日：2017-04-17

Applicant: Red Hat Israel, Ltd.

Inventor： Michael Tsirkin ,  Gal Hammer

IPC: G06F9/455 ,  G06F9/445 ,  G06F12/1036 ,  G06F9/50

CPC classification number: G06F9/45558 ,  G06F8/654 ,  G06F9/45545 ,  G06F9/5016 ,  G06F12/023 ,  G06F12/1027 ,  G06F12/1036 ,  G06F2009/45562 ,  G06F2009/45583 ,  G06F2212/1044 ,  G06F2212/152

Abstract: An example method of updating a virtual machine (VM) identifier (ID) stored in a memory buffer allocated from guest memory includes supplying firmware to a guest running on a VM that is executable on a host machine. The firmware includes instructions to allocate a memory buffer. The method also includes obtaining a buffer address of the memory buffer. The memory buffer is in guest memory and stores a VM ID that identifies a first instance of the VM. The method further includes storing the buffer address into hypervisor memory. The method also includes receiving an indication that the VM ID has been updated. The method further includes using the buffer address stored in hypervisor memory to update the VM ID.

公开(公告)号：US20170228320A1

公开(公告)日：2017-08-10

申请号：US15437369

申请日：2017-02-20

Applicant: VMware, Inc.

Inventor： Vyacheslav Vladimirovich MALYUGIN ,  Boris WEISSMAN ,  Ganesh VENKITACHALAM ,  Min XU

IPC: G06F12/1027 ,  G06F12/1009 ,  G06F12/1045 ,  G06F9/455 ,  G06F12/0891

CPC classification number: G06F12/1027 ,  G06F9/45558 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/109 ,  G06F2009/45583 ,  G06F2212/152 ,  G06F2212/305 ,  G06F2212/65 ,  G06F2212/683

Abstract: The translation lookaside buffer (TLB) of a processor is kept in synchronization with a guest page table by use of an indicator referred to as a “T” bit. The T bit of the NPT/EPT entries mapping the guest page table are set when a page walk is performed on the NPT/EPT. When modifications are made to pages mapped by NPT/EPT entries with their T bit set, changes to the TLB are made so that the TLB remains in synchronization with the guest page table. Accordingly, record/replay of virtual machines of virtualized computer systems may be performed reliably with no non-determinism introduced by stale TLBs that fall out of synchronization with the guest page table.

公开(公告)号：US20170206171A1

公开(公告)日：2017-07-20

申请号：US15475718

申请日：2017-03-31

Applicant: Cavium, Inc.

Inventor： Shubhendu S. Mukherjee ,  Bryan W. Chin ,  Wilson P. Snyder, II ,  Michael Bertone ,  Richard E. Kessler ,  Christopher Mikulis

IPC: G06F12/1036 ,  G06F9/50 ,  G06F12/1009

CPC classification number: G06F12/1036 ,  G06F9/5077 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/651

Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB provides an additional cache storing collapsed translations derived from the MTLB.

公开(公告)号：US20170177532A1

公开(公告)日：2017-06-22

申请号：US15453179

申请日：2017-03-08

Applicant: Google Inc.

Inventor： Benjamin C. Serebrin

IPC: G06F13/40 ,  G06F12/10

CPC classification number: G06F13/4022 ,  G06F3/0611 ,  G06F3/0656 ,  G06F3/067 ,  G06F12/0813 ,  G06F12/0882 ,  G06F12/10 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/1081 ,  G06F12/109 ,  G06F12/1425 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/1048 ,  G06F2212/152 ,  G06F2212/154 ,  G06F2212/264 ,  G06F2212/604 ,  G06F2212/608 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/682 ,  G06F2212/683

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for storing an address in a memory of a switch. One of the systems includes a switch that receives packets from and delivers packets to devices connected to a bus without any components on the bus between the switch and each of the devices, a memory integrated into the switch to store a mapping of virtual addresses to physical addresses, and a storage medium integrated into the switch storing instructions executable by the switch to cause the switch to perform operations including receiving a response to an address translation request for a device connected to the switch by the bus, the response including a mapping of a virtual address to a physical address, and storing, in the memory, the mapping of the virtual address to the physical address in response to receiving the response.

公开(公告)号：US20170168926A1

公开(公告)日：2017-06-15

申请号：US15292583

申请日：2016-10-13

Applicant: International Business Machines Corporation

Inventor： Steven M. Partlow

IPC: G06F12/02 ,  G06F12/1036

CPC classification number: G06F12/023 ,  G06F3/0605 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0665 ,  G06F3/067 ,  G06F12/0223 ,  G06F12/0646 ,  G06F12/08 ,  G06F12/1036 ,  G06F12/12 ,  G06F17/3007 ,  G06F17/30233 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/154 ,  G06F2212/50 ,  G06F2212/657

Abstract: Address-based thresholds for freemained frames are used to determine retention actions. Based, at least in part, on a comparison of a number of freemained frames for an address space against a threshold of freemained frames for the address space, freemained frames can be retained or rejected and/or the threshold can be adjusted.

公开(公告)号：US09678890B2

公开(公告)日：2017-06-13

申请号：US14867025

申请日：2015-09-28

Applicant: Intel Corporation

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard A Uhlig ,  Scott Dion Rodgers ,  Rajesh M. Sankaran ,  Camron Rust ,  Sebastian Schoenberg

IPC: G06F12/10 ,  G06F12/1027 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/02 ,  G06F9/455 ,  G06F12/0875 ,  G06F12/1045

CPC classification number: G06F12/1027 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/45558 ,  G06F12/0246 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1054 ,  G06F2009/45583 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/7201

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

公开(公告)号：US09665499B2

公开(公告)日：2017-05-30

申请号：US14993136

申请日：2016-01-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael K. Gschwind

IPC: G06F12/10 ,  G06F3/06 ,  G06F9/455 ,  G06F12/02 ,  G06F12/1009 ,  G06F12/1018 ,  G06F12/109 ,  G06F12/1027

CPC classification number: G06F12/1009 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0664 ,  G06F3/0665 ,  G06F3/0671 ,  G06F3/0673 ,  G06F9/45533 ,  G06F9/45558 ,  G06F12/0292 ,  G06F12/1018 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/109 ,  G06F2009/45583 ,  G06F2212/1016 ,  G06F2212/151 ,  G06F2212/657 ,  G06F2212/7201 ,  G06F2212/7202

Abstract: A system configuration is provided with multiple partitions that supports different types of address translation structure formats. The configuration may include partitions that use a single level of translation and those that use a nested level of translation. Further, differing types of translation structures may be used. The different partitions are supported by a single hypervisor.

公开(公告)号：US09658792B2

公开(公告)日：2017-05-23

申请号：US14736849

申请日：2015-06-11

Applicant: International Business Machines Corporation

Inventor： Harris M. Morgenstern ,  Steven M. Partlow ,  Scott B. Tuttle ,  Elpida Tzortzatos

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02 ,  G06F12/1036 ,  G06F12/1009 ,  G06F12/1027

CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0673 ,  G06F9/4401 ,  G06F9/4403 ,  G06F12/023 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F2212/1044 ,  G06F2212/657 ,  G06F2212/68

Abstract: In one embodiment, a computer-implemented method includes receiving a large frame area (LFAREA) request, including a request for a plurality of page frame table entries (PFTEs) to back a plurality of frames in an LFAREA of main memory. Each of the plurality of frames has one of a first size and a second size, where the second size is larger than the first size. The method further includes counting how many frames in the main memory have yet to be initialized and have one of the first size and the second size. A size needed for the plurality of PFTEs is calculated, based at least in part on the counting. A storage area is reserved for the plurality of PFTEs, by a computer processor, where a size of the storage area is the size calculated based at least in part on the counting.