公开(公告)号：US20140264868A1

公开(公告)日：2014-09-18

申请号：US13834196

申请日：2013-03-15

Applicant: CREE, INC.

Inventor： Fabian Radulescu ,  Helmut Hagleitner ,  Terry Alcorn ,  William T. Pulz

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L21/76897 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76841 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/488 ,  H01L23/53247 ,  H01L23/53252 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/02313 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/04026 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/26145 ,  H01L2224/2746 ,  H01L2224/2747 ,  H01L2224/2761 ,  H01L2224/29011 ,  H01L2224/2908 ,  H01L2224/29083 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/32238 ,  H01L2224/83191 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/83897 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12032 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/0105 ,  H01L2224/27013 ,  H01L2924/00012 ,  H01L2224/27 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01022 ,  H01L2924/00

Abstract: Embodiments of a semiconductor wafer having wafer-level die attach metallization on a back-side of the semiconductor wafer, resulting semiconductor dies, and methods of manufacturing the same are disclosed. In one embodiment, a semiconductor wafer includes a semiconductor structure and a front-side metallization that includes front-side metallization elements for a number of semiconductor die areas. The semiconductor wafer also includes vias that extend from a back-side of the semiconductor structure to the front-side metallization elements. A back-side metallization is on the back-side of the semiconductor structure and within the vias. For each via, one or more barrier layers are on a portion of the back-side metallization that is within the via and around a periphery of the via. The semiconductor wafer further includes wafer-level die attach metallization on the back-side metallization other than the portions of the back-side metallization that are within the vias and around the peripheries of the vias.

Abstract translation: 公开了具有晶片级芯片的半导体晶片的实施例，其在半导体晶片的背面上附着金属化，得到的半导体晶粒及其制造方法。 在一个实施例中，半导体晶片包括半导体结构和前侧金属化，其包括用于多个半导体管芯区域的前侧金属化元件。 半导体晶片还包括从半导体结构的背面延伸到前侧金属化元件的通孔。 背面金属化在半导体结构的背面和通孔内。 对于每个通孔，一个或多个阻挡层位于背面金属化的位于通孔内部以及通孔周围的一部分上。 半导体晶片还包括在背面金属化之外的晶片级芯片附接金属化，而不是在通孔内部和周围的通孔周围的后侧金属化部分。

公开(公告)号：US20140252072A1

公开(公告)日：2014-09-11

申请号：US13931759

申请日：2013-06-28

Applicant: HON HAI PRECISION INDUSTRY CO., LTD.

Inventor： CHIH-CHEN LAI

IPC: B23K31/12

CPC classification number: B23K31/12 ,  H01L24/75 ,  H01L24/83 ,  H01L31/02 ,  H01L31/022408 ,  H01L2224/29099 ,  H01L2224/32238 ,  H01L2224/753 ,  H01L2224/75745 ,  H01L2224/7592 ,  H01L2224/83201 ,  H01L2224/838 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A device includes a vacuum nozzle, a driver, a measuring unit, and a controller. The nozzle lifts and holds a photoelectric element having a first electrode and a second electrode. The driver drives the nozzle to press the photoelectric element onto a substrate having a soldering pad and a contact, such that the second electrode is electrically connected to the soldering pad via a layer of conductive glue.The measuring unit measures a resistance across the first electrode and the contact of the substrate when the photoelectric element is pressed onto the substrate. The controller controls the driver to drive the nozzle to keep pressing the photoelectric element harder and harder into the substrate until the resistance stops decreasing, that is, when the layer of conductive glue is at its thinnest.

Abstract translation: 装置包括真空喷嘴，驱动器，测量单元和控制器。 喷嘴提升并保持具有第一电极和第二电极的光电元件。 驱动器驱动喷嘴将光电元件按压到具有焊盘和触点的基板上，使得第二电极经由一层导电胶电连接到焊盘。 当光电元件被压在基板上时，测量单元测量跨越第一电极的电阻和基板的接触。 控制器控制驱动器驱动喷嘴，使光电元件更坚硬地压入基板，直到电阻停止下降，即当导电胶层处于最薄时。

公开(公告)号：US20140097548A1

公开(公告)日：2014-04-10

申请号：US14049243

申请日：2013-10-09

Applicant: Kyoung Hun SHIN ,  Do Hyun PARK ,  Hyun Joo SEO ,  Young Ju SHIN ,  Kyu Bong KIM ,  Woo Jun LIM

Inventor： Kyoung Hun SHIN ,  Do Hyun PARK ,  Hyun Joo SEO ,  Young Ju SHIN ,  Kyu Bong KIM ,  Woo Jun LIM

IPC: H01L23/00

CPC classification number: H01B1/22 ,  C09J2201/602 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/2939 ,  H01L2224/29393 ,  H01L2224/294 ,  H01L2224/29439 ,  H01L2224/29444 ,  H01L2224/29447 ,  H01L2224/29455 ,  H01L2224/29464 ,  H01L2224/32135 ,  H01L2224/32225 ,  H01L2224/81903 ,  H01L2224/83201 ,  H01L2224/8385 ,  H01L2224/9211 ,  H01L2924/07802 ,  H01L2924/07811 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/83

Abstract: A semiconductor device connected using an anisotropic conductive adhesive composition, the anisotropic conductive adhesive composition including a thermosetting polymerization initiator; and tetrahydrofurfuryl (meth)acrylate or furfuryl (meth)acrylate, wherein the tetrahydrofurfuryl (meth)acrylate or furfuryl (meth)acrylate is present in the composition in an amount of 1 wt % to 25 wt %, based on the total weight of the composition in terms of solid content.

Abstract translation: 使用各向异性导电粘合剂组合物连接的半导体器件，所述各向异性导电粘合剂组合物包含热固性聚合引发剂; （甲基）丙烯酸四氢糠酯或（甲基）丙烯酸糠酯，其中（甲基）丙烯酸四氢糠酯或（甲基）丙烯酸糠酯以组合物中总重量的1重量％至25重量％的量存在于组合物中 组合固体含量。

公开(公告)号：US20130343006A1

公开(公告)日：2013-12-26

申请号：US13996497

申请日：2011-12-09

Applicant: Claus Reitlinger ,  Thomas Kerssebrock ,  Thomas Klingl ,  Felix Hudlberger ,  Frank Rehme ,  Michael Gerner

Inventor： Claus Reitlinger ,  Thomas Kerssebrock ,  Thomas Klingl ,  Felix Hudlberger ,  Frank Rehme ,  Michael Gerner

IPC: H05K7/02

CPC classification number: H05K7/026 ,  H01L23/053 ,  H01L23/10 ,  H01L23/544 ,  H01L23/552 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L2223/54486 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/29 ,  H01L2224/2902 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/73253 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/83007 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83201 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/92225 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01052 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/12042 ,  H05K3/303 ,  H05K2201/1056 ,  H05K2201/10568 ,  Y02P70/613 ,  Y10T29/49002 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929

Abstract: The invention relates to an electrical module (100) for being received by automatic placement machines by means of generating a vacuum, comprising a carrier substrate (10), at least one component (20, 21) disposed on the carrier substrate (10), and a cover element (30) disposed above the at least one component (20, 21). A fixing component (40) by which the cover element (30) is attached to the at least one component (21) is disposed between the cover element (30) and the at least one component (21). The cover element can be implemented as a dimensionally stable, flat film by means of which it is possible to suction the module by means of vacuum for a placement method, and to place said module at a position on a circuit board.

Abstract translation: 本发明涉及一种电气模块（100），用于通过产生真空来由自动放置机器接收，该模块包括载体基板（10），设置在载体基板（10）上的至少一个部件（20,21） 以及设置在所述至少一个部件（20,21）上方的覆盖元件（30）。 覆盖元件（30）与所述至少一个部件（21）之间设置有固定部件（40），所述固定部件（40）通过所述固定部件（40）与所述至少一个部件（21）相连。 覆盖元件可以实现为尺寸稳定的平坦膜，通过该膜可以通过用于放置方法的真空抽吸模块，并将所述模块放置在电路板上的位置。

公开(公告)号：US08501879B2

公开(公告)日：2013-08-06

申请号：US13221547

申请日：2011-08-30

Applicant: Kazunori Kondo ,  Michihiro Sugo ,  Hideto Kato

Inventor： Kazunori Kondo ,  Michihiro Sugo ,  Hideto Kato

IPC: C08G83/00 ,  C08G77/20 ,  C08L83/14 ,  C08F299/08

CPC classification number: H01L23/293 ,  C08G77/14 ,  C08G77/52 ,  C08L63/00 ,  C08L83/14 ,  C09J163/00 ,  C09J183/14 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/3164 ,  H01L23/556 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/27003 ,  H01L2224/27436 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/2939 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/8113 ,  H01L2224/81193 ,  H01L2224/8313 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83201 ,  H01L2224/8385 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/15788 ,  H05K3/305 ,  H05K2201/10674 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2924/01047 ,  H01L2924/00014

Abstract: A semiconductor apparatus adhesive composition having excellent adhesion properties when pressure-bonded and has excellent connection reliability and insulation reliability when hardened and an adhesive sheet using this adhesive composition. An adhesive composition including: (A) a silicone resin constituted of a repeating unit represented by the following general formula (1); (B) a thermosetting resin; and (C) a compound having a flux activity, where R1 to R4 represent univalent hydrocarbon groups having carbon numbers from 1 to 8, which are equal to or different from each other; each of l and m is an integer from 1 to 100; each of a, b, c, and d is 0 or a positive number and meets 0

Abstract translation: 一种半导体装置粘合剂组合物，当粘合时具有优异的粘合性能，并且当硬化时具有优异的连接可靠性和绝缘可靠性，以及使用该粘合剂组合物的粘合 一种粘合剂组合物，其包含：（A）由以下通式（1）表示的重复单元构成的有机硅树脂; （B）热固性树脂; 和（C）具有助焊剂活性的化合物，其中R 1至R 4表示碳数为1至8的一价烃基，它们彼此相同或不同; 1和m各自为1至100的整数; a，b，c和d中的每一个为0或正数，满足0 <（c + d）/（a + b + c + d） 并且X和Y各自为二价有机基团。

公开(公告)号：US08399996B2

公开(公告)日：2013-03-19

申请号：US13204051

申请日：2011-08-05

Applicant: Khalil Hosseini ,  Joachim Mahler

Inventor： Khalil Hosseini ,  Joachim Mahler

IPC: H01L23/498

CPC classification number: H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/32506 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/83801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15747 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/00014 ,  H01L2924/00015

Abstract: Electronic circuit arrangement, includes a chip and a chip carrier having a substrate and a chip contact location. At least the chip contact location is provided with a soldering layer. The chip includes a bonding layer. A silver layer for eutectic bonding with the bonding layer is provided on the soldering layer in the region of the chip contact location.

Abstract translation: 电子电路装置包括具有衬底和芯片接触位置的芯片和芯片载体。 至少芯片接触位置设置有焊接层。 芯片包括结合层。 在芯片接触位置的区域中的焊接层上设置有用于与接合层共晶接合的银层。

公开(公告)号：US08039971B2

公开(公告)日：2011-10-18

申请号：US11752147

申请日：2007-05-22

Applicant: Khalil Hosseini ,  Joachim Mahler

Inventor： Khalil Hosseini ,  Joachim Mahler

IPC: H01L23/48

CPC classification number: H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/32506 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/83801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15747 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/00014 ,  H01L2924/00015

Abstract: Electronic circuit arrangement, includes a chip and a chip carrier having a substrate and a chip contact location. At least the chip contact location is provided with a soldering layer. The chip includes a bonding layer. A silver layer for eutectic bonding with the bonding layer is provided on the soldering layer in the region of the chip contact location.

Abstract translation: 电子电路装置包括具有衬底和芯片接触位置的芯片和芯片载体。 至少芯片接触位置设置有焊接层。 芯片包括结合层。 在芯片接触位置的区域中的焊接层上设置有用于与接合层共晶接合的银层。

公开(公告)号：US07939369B2

公开(公告)日：2011-05-10

申请号：US12465839

申请日：2009-05-14

Applicant: Mukta G. Farooq ,  Subramanian S. Iyer

Inventor： Mukta G. Farooq ,  Subramanian S. Iyer

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L24/94 ,  H01L21/76898 ,  H01L21/8221 ,  H01L24/16 ,  H01L24/28 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/80345 ,  H01L2224/80357 ,  H01L2224/80801 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83201 ,  H01L2224/83801 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105

Abstract: A method of making 3D integrated circuits and a 3D integrated circuit structure. There is a first semiconductor structure joined to a second semiconductor structure. Each semiconductor structure includes a semiconductor wafer, a front end of the line (FEOL) wiring on the semiconductor wafer, a back end of the line (BEOL) wiring on the FEOL wiring, an insulator layer on the BEOL wiring and a metallic layer on the insulator layer. The first semiconductor structure is aligned with the second semiconductor structure such that the metallic layers of each of the semiconductor structures face each other. The metallic layers of each of the semiconductor structures are in contact with and bonded to each other by a metal to metal bond wherein the bonded metallic layers form an electrically isolated layer.

Abstract translation: 制作3D集成电路和3D集成电路结构的方法。 连接到第二半导体结构的第一半导体结构。 每个半导体结构包括半导体晶片，半导体晶片上的线的前端（FEOL）布线，FEOL布线上的线的后端（BEOL）布线，BEOL布线上的绝缘体层和金属层 绝缘体层。 第一半导体结构与第二半导体结构对准，使得每个半导体结构的金属层彼此面对。 每个半导体结构的金属层通过金属 - 金属键彼此接触并彼此结合，其中结合的金属层形成电隔离层。

公开(公告)号：US20100187563A1

公开(公告)日：2010-07-29

申请号：US12691947

申请日：2010-01-22

Applicant: Masafumi Kuramoto ,  Satoru Ogawa ,  Miki Niwa

Inventor： Masafumi Kuramoto ,  Satoru Ogawa ,  Miki Niwa

IPC: H01L33/00 ,  H01L21/60

CPC classification number: H01L33/44 ,  H01L23/08 ,  H01L23/293 ,  H01L23/49579 ,  H01L23/49582 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/83 ,  H01L33/62 ,  H01L2224/05568 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/2712 ,  H01L2224/2745 ,  H01L2224/275 ,  H01L2224/29023 ,  H01L2224/2908 ,  H01L2224/29083 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29187 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73265 ,  H01L2224/83048 ,  H01L2224/83055 ,  H01L2224/83075 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/83205 ,  H01L2224/83207 ,  H01L2224/83439 ,  H01L2224/83487 ,  H01L2224/8383 ,  H01L2224/8384 ,  H01L2224/83894 ,  H01L2224/83895 ,  H01L2224/83896 ,  H01L2224/83907 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01063 ,  H01L2924/01064 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01105 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/0541 ,  H01L2924/0665 ,  H01L2924/09701 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/201 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20108 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/3025 ,  H01L2933/0066 ,  H01S5/0226 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/48 ,  H01L2224/05599

Abstract: An object of the invention is to provide a method for producing a conductive member having low electrical resistance, and the conductive member is obtained using a low-cost stable conductive material composition that does not contain an adhesive. A method for producing a semiconductor device in which silver or silver oxide provided on a surface of a base and silver or silver oxide provided on a surface of a semiconductor element are bonded, includes the steps of arranging a semiconductor element on a base such that silver or silver oxide provided on a surface of the semiconductor element is in contact with silver or silver oxide provided on a surface of the base, temporarily bonding the semiconductor element and the base by applying a pressure or an ultrasonic vibration to the semiconductor element or the base, and permanently bonding the semiconductor element and the base by applying heat having a temperature of 150 to 900° C. to the semiconductor device and the base.

Abstract translation: 本发明的目的是提供一种用于制造具有低电阻的导电构件的方法，并且使用不含粘合剂的低成本稳定的导电材料组合物获得导电构件。 一种制造半导体器件的方法，其中设置在基底表面上的银或氧化银和设置在半导体元件的表面上的银或银氧化物结合，包括以下步骤：将半导体元件布置在基底上，使得银 或设置在半导体元件的表面上的氧化银与设置在基板的表面上的银或氧化银接触，通过向半导体元件或基底施加压力或超声波振动来临时接合半导体元件和基座 并且通过向半导体器件和基底施加温度为150至900℃的热而将半导体元件和基底永久地接合。

公开(公告)号：US20070284757A1

公开(公告)日：2007-12-13

申请号：US11752147

申请日：2007-05-22

Applicant: Khalil Hosseini ,  Joachim Mahler

Inventor： Khalil Hosseini ,  Joachim Mahler

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/32506 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/83801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15747 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/00014 ,  H01L2924/00015

Abstract: Electronic circuit arrangement, includes a chip and a chip carrier having a substrate and a chip contact location. At least the chip contact location is provided with a soldering layer. The chip includes a bonding layer. A silver layer for eutectic bonding with the bonding layer is provided on the soldering layer in the region of the chip contact location.

Abstract translation: 电子电路装置包括具有衬底和芯片接触位置的芯片和芯片载体。 至少芯片接触位置设置有焊接层。 芯片包括结合层。 在芯片接触位置的区域中的焊接层上设置有用于与接合层共晶接合的银层。