公开(公告)号：US09231809B2

公开(公告)日：2016-01-05

申请号：US13730941

申请日：2012-12-29

Applicant: Shahrnaz Azizi ,  Eldad Perahia ,  Thomas J. Kenney

Inventor： Shahrnaz Azizi ,  Eldad Perahia ,  Thomas J. Kenney

IPC: H04L27/26 ,  H04L5/00 ,  H04L25/03 ,  H04L25/02

CPC classification number: H04L27/2647 ,  H04L1/205 ,  H04L1/206 ,  H04L5/0048 ,  H04L25/0204 ,  H04L25/0224 ,  H04L25/03159 ,  H04L27/2657 ,  H04L27/2675 ,  H04L2025/03414

Abstract: Logic may determine phase correction information from pilot tones. Logic may determine phase correction information from some of the pilot locations. Logic may process the shifting pilot tones for less than all of the pilot tones. Logic may process pilot tones at any location within orthogonal frequency division multiplexing (OFDM) packet. Logic may determine to process only pilot tones at the even or odd symbol indices or subcarriers. And logic may transmit a packet with a frame with a capabilities information field comprising an indication that a receiver may can process shifting pilot tones for phase tracking.

Abstract translation: 逻辑可以确定来自导频音的相位校正信息。 逻辑可以确定来自一些导频位置的相位校正信息。 逻辑可以处理少于所有导频音调的移动导频音。 逻辑可以在正交频分复用（OFDM）分组内的任何位置处理导频音。 逻辑可以确定仅在偶或奇符号索引或子载波处理导频音。 并且逻辑可以用具有能力信息字段的帧发送分组，能力信息字段包括接收机可以处理用于相位跟踪的移位导频音的指示。

公开(公告)号：US20150381451A1

公开(公告)日：2015-12-31

申请号：US14747993

申请日：2015-06-23

Applicant: ADVA Optical Networking SE

Inventor： Georgy Kolotov ,  Opher Ronen ,  Nir Laufer ,  Israel Sasson

IPC: H04L12/26 ,  H04L7/00

CPC classification number: H04L43/0864 ,  H04J3/14 ,  H04L1/203 ,  H04L1/205 ,  H04L7/0016

Abstract: A method for use in connection with a data transmission network includes receiving a plurality of time interval error data samples over a sampling period and comparing a duration of the sampling period to a time threshold for the sampling period. If the duration of the sampling period is less than or equal to the time threshold for the sampling period, the method includes processing the received plurality of data samples so as to calculate in real time a maximum time interval error. However, if the duration of the sampling period exceeds the time threshold for the sampling period, the method includes dividing the sampling period into a finite number of sub-intervals and processing the data samples in each sub-interval so as to produce a respective intermediate result for each sub-interval. Each of these intermediate results is stored directly after it is produced, and these stored intermediate results are processed so as to estimate the maximum time interval error.

Abstract translation: 一种与数据传输网络结合使用的方法包括在采样周期内接收多个时间间隔误差数据采样，并将采样周期的持续时间与采样周期的时间阈值进行比较。 如果采样周期的持续时间小于或等于采样周期的时间阈值，则该方法包括处理所接收的多个数据样本，以实时计算最大时间间隔误差。 然而，如果采样周期的持续时间超过采样周期的时间阈值，则该方法包括将采样周期划分​​为有限数量的子间隔并且处理每个子间隔中的数据样本，以便产生相应的中间 每个子间隔的结果。 这些中间结果中的每一个都直接存储在其产生之后，并且处理这些存储的中间结果以估计最大时间间隔误差。

公开(公告)号：US20150372804A1

公开(公告)日：2015-12-24

申请号：US14722995

申请日：2015-05-27

Applicant: Rambus Inc.

Inventor： Srinivasaraman Chandrasekaran ,  Kunal Desai

IPC: H04L7/00 ,  H04L1/20

CPC classification number: H04L1/205 ,  G01R31/31709 ,  G01R31/31726 ,  H04L1/241 ,  H04L1/242 ,  H04L7/0079 ,  H04L7/0083 ,  H04L7/10

Abstract: An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.

Abstract translation: 集成电路包括多个接收器，每个接收器具有时钟和数据恢复电路。 可以使第一接收机中的第一本地时钟恢复电路产生模拟要测试的条件的测试时钟，并且使包括第二本地时钟恢复电路在内的多个接收机中的第二接收机使用该测试 时钟代替参考时钟，同时在其输入端接收测试数据序列。 接收机中的时钟和数据恢复电路可以包括响应于环路控制信号的时钟控制环路，以响应于（i）用于正常操作或在测试期间的相应数据信号中的选择性的一个来选择性地修改所选择的参考时钟以产生本地时钟 ，以及（ii）施加到时钟控制回路的测试信号，在这种情况下产生测试时钟。

公开(公告)号：US09209818B2

公开(公告)日：2015-12-08

申请号：US14544382

申请日：2014-12-30

Applicant: Parade Technologies, Ltd.

Inventor： Ming Qu ,  Yuanping Chen ,  Yuntao Zhu ,  Quan Yu ,  Kochung Lee

IPC: H03L7/087 ,  H04B17/00 ,  H04L1/20 ,  H04L7/033 ,  H03L7/08 ,  H03L7/081 ,  H03L7/099 ,  G01R29/26

CPC classification number: H03L7/087 ,  G01R29/26 ,  H03L7/0807 ,  H03L7/081 ,  H03L7/0998 ,  H04B17/104 ,  H04L1/205 ,  H04L1/243 ,  H04L7/033

Abstract: A system and method are disclosed for performing on die jitter tolerance testing. A set of clocks are generated based on an input signal. The set of clocks include in an in-phase signal based on the data switching edge of the input signal. Additionally, the set of clocks include an inverted clock phase shifted by 180 degrees, and a pair of clocks phase shifted positively and negatively by a certain number of degrees, θ. Data input is sampled based on the inverted clock and the two phase shifted clocks. The eye opening of the input signal can be determined based on whether each of the inverted clock and the two phase shifted clocks sample the correct data from the input signal at various θ values.

公开(公告)号：US20150350042A1

公开(公告)日：2015-12-03

申请号：US14819798

申请日：2015-08-06

Applicant: Tektronix, Inc.

Inventor： Pavel R. Zivny ,  Maria Agoston ,  Kan Tan

IPC: H04L12/26

CPC classification number: H04L43/087 ,  H04L1/205 ,  H04L43/045

Abstract: Method and systems are described for estimating signal impairments, in particular jitter that includes uncorrelated, non-periodic signal impairments. One system may take the form of an oscilloscope. The estimates may take the form of a probability density function (PDF) for uncorrelated signal impairments that has been modified to replace low probability regions with a known approximation and an extrapolation of the known approximation.

Abstract translation: 描述了用于估计信号损伤的方法和系统，特别是包括不相关的非周期信号损伤的抖动。 一个系统可能采用示波器的形式。 估计可以采用未相关信号损伤的概率密度函数（PDF）的形式，其已经被修改以用已知近似的已知近似和外推来代替低概率区域。

公开(公告)号：US09184904B2

公开(公告)日：2015-11-10

申请号：US14513782

申请日：2014-10-14

Applicant: FUJITSU LIMITED

Inventor： Yoshiyasu Doi

IPC: H04L7/00 ,  H04L7/04

CPC classification number: H04L7/0012 ,  H03L7/00 ,  H04L1/20 ,  H04L1/205 ,  H04L7/0087 ,  H04L7/0331 ,  H04L7/043 ,  H04L25/03057 ,  H04L25/068 ,  H04L25/069 ,  H04L25/14

Abstract: A communication system includes: a plurality of lanes; a plurality of transmission circuits respectively outputting data to the lanes in accordance with a transmission clock; and a plurality of reception circuits respectively receiving data from the lanes, each reception circuit includes: a clock data recovery circuit extracting own clock information from received data: a clock information switch circuit selecting either one of the own clock information of the reception circuit or another own clock information of an another reception circuit; a phase shifter generating a phase adjusted clock from a common reception clock source in accordance with clock information selected by the clock information switch circuit; and an input circuit taking in transmitted data in accordance with the adjusted clock, and the clock information switch circuit selects the own clock information in a normal operation and selects the another own clock information in an eye-opening measurement operation.

Abstract translation: 通信系统包括：多个车道; 多个发送电路，根据传输时钟分别向车道输出数据; 分别从通道接收数据的多个接收电路，每个接收电路包括：时钟数据恢复电路，从接收到的数据中提取自己的时钟信息：时钟信息切换电路，选择接收电路或另一个的自己的时钟信息 自己的另一个接收电路的时钟信息; 移相器，根据由时钟信息切换电路选择的时钟信息，从公共接收时钟源产生相位调整时钟; 以及根据调整后的时钟接收发送数据的输入电路，并且时钟信息切换电路在正常操作中选择自己的时钟信息，并且在开眼测量操作中选择另一个自己的时钟信息。

公开(公告)号：US20150280870A1

公开(公告)日：2015-10-01

申请号：US14722511

申请日：2015-05-27

Applicant: Futurewei Technologies, Inc.

Inventor： Hiroshi Takatori ,  Kofi Anim-Appiah ,  Hang Yan

IPC: H04L1/24 ,  H04B17/11 ,  H04B17/336 ,  H04L1/00

CPC classification number: H04L1/0042 ,  H04B17/11 ,  H04B17/336 ,  H04L1/205 ,  H04L1/24 ,  H04L1/242 ,  H04L1/243 ,  H04L1/244 ,  H04L25/03343

Abstract: A transmitter including a noise signal generator and a summing element is provided. The noise signal generator is configured to receive multiple noise settings and output multiple noise signals corresponding to the multiple noise settings. The summing element is configured to receive a transmit data signal and the multiple noise signals, sum one or more of the multiple noise signals with the transmit data signal, and output to a transmit driver configured to generate one of a single-ended and a differential signal based on the sum of the one or more of the multiple noise signals with the transmit data signal.

Abstract translation: 提供包括噪声信号发生器和求和元件的发射机。 噪声信号发生器被配置为接收多个噪声设置并输出对应于多个噪声设置的多个噪声信号。 所述求和元件被配置为接收发射数据信号和所述多个噪声信号，用所述发射数据信号求和所述多个噪声信号中的一个或多个，并将其输出到被配置为产生单端和差分 基于多个噪声信号中的一个或多个与发送数据信号的和的信号。

公开(公告)号：US09071407B2

公开(公告)日：2015-06-30

申请号：US13846491

申请日：2013-03-18

Applicant: Rambus Inc.

Inventor： Srinivasaraman Chandrasekaran ,  Kunal Desai

IPC: H04B3/46 ,  H04L7/00 ,  H04L7/10 ,  G01R31/317 ,  H04L1/20 ,  H04L1/24

CPC classification number: H04L1/205 ,  G01R31/31709 ,  G01R31/31726 ,  H04L1/241 ,  H04L1/242 ,  H04L7/0079 ,  H04L7/0083 ,  H04L7/10

Abstract: An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.

Abstract translation: 集成电路包括多个接收器，每个接收器具有时钟和数据恢复电路。 可以使第一接收机中的第一本地时钟恢复电路产生模拟要测试的条件的测试时钟，并且使包括第二本地时钟恢复电路在内的多个接收机中的第二接收机使用该测试 时钟代替参考时钟，同时在其输入端接收测试数据序列。 接收机中的时钟和数据恢复电路可以包括响应于环路控制信号的时钟控制环路，以响应于（i）用于正常操作或在测试期间的相应数据信号中的选择性的一个来选择性地修改所选择的参考时钟以产生本地时钟 ，以及（ii）施加到时钟控制回路的测试信号，在这种情况下产生测试时钟。

公开(公告)号：US20150098538A1

公开(公告)日：2015-04-09

申请号：US14507702

申请日：2014-10-06

Applicant: QUALCOMM Incorporated

Inventor： George Alan Wiley ,  Chulkyu Lee

IPC: H04L7/04

CPC classification number: H04L7/042 ,  H04L1/205 ,  H04L1/206 ,  H04L1/247 ,  H04L5/20 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0294 ,  H04L25/0298 ,  H04L25/4917

Abstract: System, methods and apparatus are described that facilitate tests and measurements related to multi-wire, multi-phase communications links. Information is transmitted in N-phase polarity encoded symbols and an eye pattern corresponding to the symbols may be generated such that the symbols are aligned with a trigger for each symbol that corresponds to a clock edge used to sample the symbols. The eye pattern may be used to determine sufficiency of setup times in the communication links and other such characteristics defining a communications channel capabilities.

Abstract translation: 描述了便于与多线，多相通信链路相关的测试和测量的系统，方法和装置。 信息以N相极性编码符号发送，并且可以生成与符号相对应的眼图，使得符号与对应于用于采样符号的时钟边缘的每个符号的触发对齐。 眼图可以用于确定通信链路中的建立时间的充分性以及定义通信信道能力的其它这样的特性。

公开(公告)号：US08971468B1

公开(公告)日：2015-03-03

申请号：US14064539

申请日：2013-10-28

Applicant: Xilinx, Inc.

Inventor： Paolo Novellini

IPC: H04L7/00 ,  H04L1/00

CPC classification number: H04L1/205 ,  H04L1/0071

Abstract: The methods and apparatus disclosed herein provide an operative system for increasing the resolution of serial DRUs based on interleaved free running oversamplers. In particular, this system uses incoming data to measure and to compensate the skew between two or more free running oversamplers (e.g., SerDes), without the need for any hardware design requirement relating to the precision of the relative skew of the oversamplers.

Abstract translation: 本文公开的方法和装置提供了一种用于基于交错自由运行的过采样器来增加串行DRU的分辨率的操作系统。 特别地，该系统使用输入数据来测量和补偿两个或更多个自由运行的过采样器（例如，SerDes）之间的偏斜，而不需要与过采样器的相对偏斜的精度相关的任何硬件设计要求。