公开(公告)号：US12222611B2

公开(公告)日：2025-02-11

申请号：US18182268

申请日：2023-03-10

Applicant: PARADE TECHNOLOGIES, LTD

Inventor： You Ben Yin ,  Quan Yu ,  Yueh-Lin Yang

IPC: G02F1/1345 ,  G02F1/1333 ,  G06F3/041 ,  G06F3/044

Abstract: An electronic device has a display substrate including a display area, a driver area, and a fan-out area. The fan-out area is divided to a plurality of fan-out regions, and has interconnects configured to access display elements formed on the display area. The driver area is adjacent to the fan-out area and configured to receive a driver chip having a plurality of pads. The interconnects of the fan-out area include a subset of first interconnects. Each first interconnect passes a first fan-out region and a second fan-out region to access a respective display element. A first portion of the subset of first interconnects is formed on the first fan-out region with a first interconnect pitch, and a second portion of the subset of first interconnects is formed on the second fan-out region with a second interconnect pitch different from the first interconnect pitch.

公开(公告)号：US09418607B2

公开(公告)日：2016-08-16

申请号：US13961035

申请日：2013-08-07

Applicant: Parade Technologies, Ltd.

Inventor： Ta-Tao Hsu ,  Quan Yu ,  Yueh-Lin Yang

IPC: G09G3/36 ,  G09G3/20

CPC classification number: G09G3/3611 ,  G09G3/2092 ,  G09G2310/0213 ,  G09G2330/021

Abstract: A system and method are disclosed to utilize Gray code in order to reduce the power consumption of column drivers in a display system. Binary source data is received from a timing controller. A Gray code digitizer converts and encodes the binary source data into a binary portion of data and a Gray code data. The binary portion data and the Gray code data are transmitted through a shift register to a digital-to-analog converter. The shift register consumes less power processing the converted binary portion of data and Gray code data than the corresponding binary source data. The digital-to-analog converter decodes the Gray code and generates corresponding gamma voltage levels for display use.

Abstract translation: 公开了一种利用格雷码来降低显示系统中列驱动器的功耗的系统和方法。 从定时控制器接收二进制源数据。 格雷码数字转换器将二进制源数据转换并编码为二进制数据部分和格雷码数据。 二进制部分数据和格雷码数据通过移位寄存器传输到数模转换器。 与对应的二进制源数据相比，移位寄存器消耗更少的处理数据和格雷码数据的二进制部分的功率。 数模转换器解码格雷码，并产生相应的伽玛电压电平供显示使用。

公开(公告)号：US11592715B2

公开(公告)日：2023-02-28

申请号：US17334370

申请日：2021-05-28

Applicant: PARADE TECHNOLOGIES, LTD.

Inventor： Yueh-Lin Yang ,  Quan Yu ,  Haijun Chen ,  Tatao Hsu ,  Jonathan Huang

IPC: G02F1/1345 ,  G09G3/36 ,  G06F3/041 ,  G06F3/044

Abstract: An electronic device has a display screen and a driver chip disposed on a driver area of the display screen. A fan-out area of the display screen has interconnects configured to provide electrical accesses to display elements of the display area. The driver chip includes a first edge, a second edge, and a row of electronic pads proximate to the first edge. The electronic pads have a first subset of end pads at a first end of the first row, a second subset of end pads at a second opposite end of the first row, and a subset of intermediate pads located between the first subset and second subset of end pads. The first subset of end pads physically contact a first subset of interconnects from the first edge, and the subset of intermediate pads physically contact a second subset of interconnects from the one or more second edges.

公开(公告)号：US20180190220A1

公开(公告)日：2018-07-05

申请号：US15904212

申请日：2018-02-23

Applicant: Parade Technologies, Ltd.

Inventor： Quan Yu ,  Ta-tao Hsu ,  Yueh-lin Yang ,  Haijun Chen ,  Kuo-cheng Huang ,  Nelson Rao

IPC: G09G3/36

CPC classification number: G09G3/3614 ,  G09G3/2092 ,  G09G3/3611 ,  G09G3/3685 ,  G09G2310/08 ,  G09G2330/021

Abstract: A method including receiving a first row of display data for a first time period, and determining a value of a specified bit position for first portions of a first plurality of multi-bit portions in the first row. The method further includes receiving a second row of display data for a second time period, and determining a value of the specified bit position for second portions of a second plurality of multi-bit portions in the second row. Based on the determining, identifying second portions that indicate a change in the value of the specified bit position from the first time period to the second time period, and identifying an output channel associated with each identified portion. The method further includes grouping each identified output channel into a first or second group based on a polarity type, and connecting the identified output channels together within each group.

公开(公告)号：US09209818B2

公开(公告)日：2015-12-08

申请号：US14544382

申请日：2014-12-30

Applicant: Parade Technologies, Ltd.

Inventor： Ming Qu ,  Yuanping Chen ,  Yuntao Zhu ,  Quan Yu ,  Kochung Lee

IPC: H03L7/087 ,  H04B17/00 ,  H04L1/20 ,  H04L7/033 ,  H03L7/08 ,  H03L7/081 ,  H03L7/099 ,  G01R29/26

CPC classification number: H03L7/087 ,  G01R29/26 ,  H03L7/0807 ,  H03L7/081 ,  H03L7/0998 ,  H04B17/104 ,  H04L1/205 ,  H04L1/243 ,  H04L7/033

Abstract: A system and method are disclosed for performing on die jitter tolerance testing. A set of clocks are generated based on an input signal. The set of clocks include in an in-phase signal based on the data switching edge of the input signal. Additionally, the set of clocks include an inverted clock phase shifted by 180 degrees, and a pair of clocks phase shifted positively and negatively by a certain number of degrees, θ. Data input is sampled based on the inverted clock and the two phase shifted clocks. The eye opening of the input signal can be determined based on whether each of the inverted clock and the two phase shifted clocks sample the correct data from the input signal at various θ values.

公开(公告)号：US20230229044A1

公开(公告)日：2023-07-20

申请号：US18182268

申请日：2023-03-10

Applicant: PARADE TECHNOLOGIES, LTD

Inventor： You Ben Yin ,  Quan Yu ,  Yueh-Lin Yang

IPC: G02F1/1345 ,  G02F1/1333 ,  G06F3/041 ,  G06F3/044

CPC classification number: G02F1/13452 ,  G02F1/13458 ,  G02F1/13338 ,  G06F3/04166 ,  G06F3/0412 ,  G06F3/0443

Abstract: An electronic device has a display substrate including a display area, a driver area, and a fan-out area. The fan-out area is divided to a plurality of fan-out regions, and has interconnects configured to access display elements formed on the display area. The driver area is adjacent to the fan-out area and configured to receive a driver chip having a plurality of pads. The interconnects of the fan-out area include a subset of first interconnects. Each first interconnect passes a first fan-out region and a second fan-out region to access a respective display element. A first portion of the subset of first interconnects is formed on the first fan-out region with a first interconnect pitch, and a second portion of the subset of first interconnects is formed on the second fan-out region with a second interconnect pitch different from the first interconnect pitch.

公开(公告)号：US20210397324A1

公开(公告)日：2021-12-23

申请号：US16908534

申请日：2020-06-22

Applicant: Parade Technologies, Ltd.

Inventor： Quan Yu ,  Zhengyu Yuan ,  Ross Fosler ,  Denis Ellis ,  Zhiqiang Huang ,  Roel Coppoolse

IPC: G06F3/041 ,  G06F3/044

Abstract: This application is directed to intra-panel communication in a touch display device in which a touch-integrated timing controller (TTCON) is coupled to touch-embedded source drivers (TSDs) via a plurality of forward links and a set of backward links. The forward links include a first subset of display forward links and a second subset of touch forward links. The TSDs are electrically coupled to a display panel including a plurality of display pixels and a plurality of touch sensors. The TTCON sends a display drive signal including display content data and display control data over the display forward links, and sends a touch control signal including an instruction to initiate an operation mode over the touch forward links. Upon receiving the touch control signal, the TSDs identify the instruction to initiate the operation mode, generate touch data accordingly, and return the touch data to the TTCON via the backward links.

公开(公告)号：US20180182329A1

公开(公告)日：2018-06-28

申请号：US15904208

申请日：2018-02-23

Applicant: Parade Technologies, Ltd.

Inventor： Quan Yu ,  CuiHua Jia ,  Ta-Tao Hsu ,  Yueh-Lin Yang ,  Haijun Chen ,  Kuo-Cheng Huang

IPC: G09G3/36

CPC classification number: G09G3/3614 ,  G09G3/3685 ,  G09G3/3688 ,  G09G2310/0297 ,  G09G2330/021

Abstract: A method including receiving information and a row of display data for display on a row of a display panel, sending the data to channels in accordance with the information, each channel supplying a portion of the row of display data to a column of pixels in the display panel using one a source driver, outputting, by a plurality of source drivers, the row of display data to the row of the display panel, and receiving a row completion indicator subsequent to the outputting. The method further includes determining, during a polarity period, a polarity state of a portion of the row of display data, identifying a group of source drivers, generating charge sharing enable signal(s) using the row completion indicator, and connecting outputs of source drivers in the identified group of source drivers together during the polarity period using the charge sharing enable signal(s).

公开(公告)号：US09361838B2

公开(公告)日：2016-06-07

申请号：US13961035

申请日：2013-08-07

Applicant: Parade Technologies, Ltd.

Inventor： Ta-Tao Hsu ,  Quan Yu ,  Yueh-Lin Yang

IPC: G09G3/36 ,  G09G3/20

Abstract: A system and method are disclosed to utilize Gray code in order to reduce the power consumption of column drivers in a display system. Binary source data is received from a timing controller. A Gray code digitizer converts and encodes the binary source data into a binary portion of data and a Gray code data. The binary portion data and the Gray code data are transmitted through a shift register to a digital-to-analog converter. The shift register consumes less power processing the converted binary portion of data and Gray code data than the corresponding binary source data. The digital-to-analog converter decodes the Gray code and generates corresponding gamma voltage levels for display use.

公开(公告)号：US20150042551A1

公开(公告)日：2015-02-12

申请号：US13961035

申请日：2013-08-07

Applicant: Parade Technologies, Ltd.

Inventor： Ta-Tao Hsu ,  Quan Yu ,  Yueh-Lin Yang

IPC: G09G3/36

CPC classification number: G09G3/3611 ,  G09G3/2092 ,  G09G2310/0213 ,  G09G2330/021

Abstract: A system and method are disclosed to utilize Gray code in order to reduce the power consumption of column drivers in a display system. Binary source data is received from a timing controller. A Gray code digitizer converts and encodes the binary source data into a binary portion of data and a Gray code data. The binary portion data and the Gray code data are transmitted through a shift register to a digital-to-analog converter. The shift register consumes less power processing the converted binary portion of data and Gray code data than the corresponding binary source data. The digital-to-analog converter decodes the Gray code and generates corresponding gamma voltage levels for display use.

Abstract translation: 公开了一种利用格雷码来降低显示系统中列驱动器的功耗的系统和方法。 从定时控制器接收二进制源数据。 格雷码数字转换器将二进制源数据转换并编码为二进制数据部分和格雷码数据。 二进制部分数据和格雷码数据通过移位寄存器传输到数模转换器。 与对应的二进制源数据相比，移位寄存器消耗更少的处理数据和格雷码数据的二进制部分的功率。 数模转换器解码格雷码，并产生相应的伽玛电压电平供显示使用。