公开(公告)号：US08065794B2

公开(公告)日：2011-11-29

申请号：US12239306

申请日：2008-09-26

Applicant: Honchin En ,  Tohru Nakai ,  Takeo Oki ,  Naohiro Hirose ,  Kouta Noda

Inventor： Honchin En ,  Tohru Nakai ,  Takeo Oki ,  Naohiro Hirose ,  Kouta Noda

IPC: H05K3/02 ,  H01K3/22

CPC classification number: H05K3/4644 ,  C23C18/1607 ,  C23C18/1653 ,  C23C18/22 ,  C23C18/30 ,  C23C18/34 ,  C23C18/405 ,  C23C28/00 ,  C23C28/023 ,  C23C28/42 ,  C25D3/38 ,  C25D5/022 ,  C25D5/18 ,  C25D5/34 ,  C25D7/123 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/241 ,  H05K3/381 ,  H05K3/382 ,  H05K3/384 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4661 ,  H05K2201/0215 ,  H05K2201/0344 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0353 ,  H05K2203/0723 ,  H05K2203/1476 ,  H05K2203/1492 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: The present invention has for its object to provide a process for manufacturing multilayer printed circuit boards which is capable of simultaneous via hole filling and formation of conductor circuit and via holes of good crystallinity and uniform deposition can be constructed on a substrate and high-density wiring and highly reliable conductor connections can be realized without annealing. The present invention is related to a process for manufacturing multilayer printed circuit boards which comprises disposing an interlayer resin insulating layer on a substrate formed with a conductor circuit, creating openings for formation of via holes in said interlayer resin insulating layer, forming an electroless plated metal layer on said interlayer resin insulating layer, disposing a resist thereon, performing electroplating, stripping the resist off and etching the electroless plated metal layer to provide a conductor circuit and via holes, wherein the electroplating is performed intermittently using said electroless plated metal layer as cathode and a plating metal as anode at a constant voltage between said anode and said cathode.

Abstract translation: 本发明的目的是提供一种制造多层印刷电路板的方法，其能够同时通孔填充和形成导体电路，并且可以在基板和高密度布线上构造具有良好结晶度和均匀沉积的通孔 并且可以实现高可靠性的导体连接而不退火。 本发明涉及一种多层印刷电路板的制造方法，其特征在于，在形成有导体电路的基板上设置层间树脂绝缘层，在所述层间树脂绝缘层上形成用于形成通孔的开口，形成无电镀金属 层，在其上设置抗蚀剂，进行电镀，剥离抗蚀剂并蚀刻无电镀金属层以提供导体电路和通孔，其中使用所述无电镀金属层作为阴极间歇地进行电镀 以及在所述阳极和所述阴极之间的恒定电压下的电镀金属作为阳极。

公开(公告)号：US20110189381A1

公开(公告)日：2011-08-04

申请号：US12696328

申请日：2010-01-29

Applicant: Dylan Joseph Boday ,  Joseph Kuczynski ,  Mark Anthony Marnell ,  Robert Ernst Meyer, III ,  Timothy Jerome Tofil

Inventor： Dylan Joseph Boday ,  Joseph Kuczynski ,  Mark Anthony Marnell ,  Robert Ernst Meyer, III ,  Timothy Jerome Tofil

IPC: B05D3/00 ,  B32B15/08 ,  B32B27/38 ,  B32B27/30 ,  C09D5/08 ,  C08G77/395

CPC classification number: H05K3/284 ,  B32B15/08 ,  B32B27/30 ,  B32B27/38 ,  C08G77/395 ,  C08K5/5313 ,  C09D5/086 ,  C09D7/63 ,  H05K3/285 ,  H05K2201/0215 ,  H05K2201/0257 ,  H05K2201/09872 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T428/31504 ,  Y10T428/31529 ,  Y10T428/31663 ,  Y10T428/31678 ,  Y10T428/31699 ,  Y10T428/31935

Abstract: An apparatus includes an electronic component mounted on a substrate and metal conductors electrically connecting the electronic component. A conformal coating overlies the metal conductors and comprises a polymer into which a phosphine compound is impregnated and/or covalently bonded. Accordingly, the conformal coating is able to protect the metal conductors from corrosion caused by sulfur components (e.g., elemental sulfur, hydrogen sulfide, and/or sulfur oxides) in the air. That is, the phosphine compound in the polymer reacts with any corrosion inducing sulfur component in the air and prevents the sulfur component from reacting with the underlying metal conductors. Preferably, the phosphine compound in the polymer does not react with other components in the air (e.g., carbon dioxide) which would otherwise deplete its availability for the target reaction. The phosphine compound may be rendered completely non-volatile by covalently bonding it directly into the polymer backbone.

Abstract translation: 一种装置包括安装在基板上的电子部件和电连接电子部件的金属导体。 保形涂层覆盖在金属导体上并且包含聚合物，磷化合物被浸渍和/或共价键合到该聚合物中。 因此，保形涂层能够保护金属导体免受空气中的硫成分（例如元素硫，硫化氢和/或硫氧化物）引起的腐蚀。 也就是说，聚合物中的膦化合物与空气中的任何腐蚀诱导硫成分反应，并防止硫成分与下面的金属导体反应。 优选地，聚合物中的膦化合物不与空气中的其它组分（例如二氧化碳）反应，否则其将耗尽其用于目标反应的可用性。 膦化合物可以通过将其直接共价键合到聚合物主链中而使其完全不挥发。

公开(公告)号：US20110141704A1

公开(公告)日：2011-06-16

申请号：US13017590

申请日：2011-01-31

Applicant: Shigenobu SEKINE ,  Yurina SEKINE ,  Yoshiharu KUWANA

Inventor： Shigenobu SEKINE ,  Yurina SEKINE ,  Yoshiharu KUWANA

IPC: H05K1/18 ,  H05K1/09 ,  H01B1/02

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H05K3/4038 ,  H05K3/4061 ,  H05K3/4614 ,  H05K2201/0215 ,  H05K2201/0218 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/083 ,  H05K2203/0285 ,  H05K2203/104 ,  H05K2203/128 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A circuit board includes a substrate, a circuit pattern and a through electrode. The circuit pattern is disposed on one side of the substrate in a thickness direction thereof. The through electrode is filled in a through-hole formed in the substrate with one end connected to the circuit pattern. The circuit pattern and the through electrode each have an area containing a noble metal component (e.g., Au component) and are connected to each other therethrough.

Abstract translation: 电路板包括基板，电路图案和通孔电极。 电路图案沿其厚度方向设置在基板的一侧。 通孔电极填充在形成在基板中的通孔中，其一端连接到电路图案。 电路图案和贯通电极各自具有含有贵金属成分（例如Au成分）的区域，并且通过其彼此连接。

公开(公告)号：US07939171B2

公开(公告)日：2011-05-10

申请号：US11018473

申请日：2004-12-22

Applicant: Hideo Aoki ,  Naoko Yamaguchi ,  Chiaki Takubo

Inventor： Hideo Aoki ,  Naoko Yamaguchi ,  Chiaki Takubo

IPC: B32B5/66

CPC classification number: H05K3/207 ,  H05K1/095 ,  H05K3/1266 ,  H05K2201/0212 ,  H05K2201/0215 ,  H05K2203/0517 ,  Y10T428/12535 ,  Y10T428/12556 ,  Y10T428/12569 ,  Y10T428/256 ,  Y10T428/2991 ,  Y10T428/2998

Abstract: Provided is metal-containing resin particle for forming a conductor pattern in which the metal particles are dispersed in a resin matrix, and the content of the metal particles is 70 wt % or less.

Abstract translation: 本发明提供用于形成金属颗粒分散在树脂基体中的金属的树脂颗粒，并且金属颗粒的含量为70重量％以下。

公开(公告)号：US07880093B2

公开(公告)日：2011-02-01

申请号：US11693107

申请日：2007-03-29

Applicant: Woong Sun Lee

Inventor： Woong Sun Lee

IPC: H05K1/03

CPC classification number: H05K3/185 ,  H01L23/13 ,  H01L23/145 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/15157 ,  H05K1/0284 ,  H05K1/0373 ,  H05K1/183 ,  H05K3/0026 ,  H05K3/0032 ,  H05K3/182 ,  H05K2201/0215 ,  H05K2201/09845 ,  H05K2203/107 ,  Y10T428/12528 ,  H01L2924/00

Abstract: A substrate for embodying multi-package comprises an underlying layer has a polymer material containing a conductive filler and provided with a step-like groove divided into step part and bottom part; a coating layer formed over the underlying layer, the coating layer is formed so that it may define a metal-wire forming area on the step part and the bottom part of the step-like groove and the conductive filler in the metal-wire forming area is exposed; and a metal wire formed via a plating process using the exposed conductive filler in the metal-wire forming area defined by the coating layer as a seed layer.

Abstract translation: 用于实施多封装的基板包括下层，其具有包含导电填料的聚合物材料，并且设置有分为台阶部分和底部的阶梯状凹槽; 形成在下层之上的涂层，形成涂层，使得其可以在台阶部分上形成金属线形成区域，并且在金属线形成区域中的阶梯状沟槽和导电填料的底部 被暴露 以及金属线，其通过使用在由涂层限定的金属线形成区域中的暴露的导电填料作为种子层的电镀工艺形成。

公开(公告)号：US20100155456A1

公开(公告)日：2010-06-24

申请号：US12536122

申请日：2009-08-05

Applicant: GARETH G. HOUGHAM ,  KAMALESH K. SRIVASTAVA ,  SUNG K. KANG ,  DA-YUAN SHIH ,  BRIAN R. SUNDLOF ,  S. JAY CHEY ,  DONALD W. HENDERSON ,  DAVID R. DI MILIA ,  RICHARD P. FERLITA ,  ROY A. CARRUTHERS

Inventor： GARETH G. HOUGHAM ,  KAMALESH K. SRIVASTAVA ,  SUNG K. KANG ,  DA-YUAN SHIH ,  BRIAN R. SUNDLOF ,  S. JAY CHEY ,  DONALD W. HENDERSON ,  DAVID R. DI MILIA ,  RICHARD P. FERLITA ,  ROY A. CARRUTHERS

IPC: B23K31/02

CPC classification number: B23K1/19 ,  B23K35/262 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/0215

Abstract: Briefly, a novel material process is disclosed wherein one or more nucleation modifiers are added, in trace amounts, to a lead-free tin-rich solder alloy to produce a solder composition with reduce or suppressed undercooling temperature characteristics. The modifier being a substance which facilitates the reduction of extreme anisotropic properties associated with body-centered-tetragonal tin based lead-free solder. The addition of the nucleation modifiers to the solder alloy does not materially effect the solder composition's melting point. As such, balls of solder with the nucleated composition freeze while other solder balls within the array remain in the melt. This effectively enables one substrate to be pinned to another substrate by one or more predetermined solder balls to secure the package while the remaining solder joints are in the liquid state. Further, the addition of a trace amount of nucleation sites within the composition facilitates control over the number, size, and orientations of primary intermetallic compounds in tin rich crystallite grains. Moreover, trace amounts of one or more solid and/or insoluble nucleating modifiers within a given volume of solder reduces the size of average crystallites within the composition.

Abstract translation: 简而言之，公开了一种新颖的材料方法，其中将一种或多种成核改性剂以微量添加到无铅富锡焊料合金中以产生具有降低或抑制的过冷温度特性的焊料组合物。 该改性剂是有助于减少与体心四方锡锡基无铅焊料相关的极端各向异性的物质。 将成核改性剂添加到焊料合金中不会实质上影响焊料组合物的熔点。 因此，具有成核组合物的焊料球冻结，而阵列内的其它焊球保持在熔体中。 这有效地使一个基板通过一个或多个预定的焊球被固定到另一个基板，以固定封装，而剩余的焊点处于液态。 此外，在组合物中添加微量的成核位点有助于控制富锡微晶颗粒中初级金属间化合物的数量，尺寸和取向。 此外，在给定体积的焊料中痕量的一种或多种固态和/或不溶性成核改性剂减少了组合物内平均微晶的尺寸。

公开(公告)号：US07703661B2

公开(公告)日：2010-04-27

申请号：US11752382

申请日：2007-05-23

Applicant: Gareth G. Hougham ,  Kamalesh K. Srivastava ,  Sung K. Kang ,  Da-Yuan Shih ,  Brian R. Sundlof ,  S. Jay Chey ,  Donald W. Henderson ,  David R. Di Milia ,  Richard P. Ferlita ,  Roy A. Carruthers

Inventor： Gareth G. Hougham ,  Kamalesh K. Srivastava ,  Sung K. Kang ,  Da-Yuan Shih ,  Brian R. Sundlof ,  S. Jay Chey ,  Donald W. Henderson ,  David R. Di Milia ,  Richard P. Ferlita ,  Roy A. Carruthers

IPC: B23K35/24

CPC classification number: B23K1/19 ,  B23K35/262 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/0215

Abstract: Briefly, a novel material process is disclosed wherein one or more nucleation modifiers are added, in trace amounts, to a lead-free tin-rich solder alloy to produce a solder composition with reduced or suppressed undercooling temperature characteristics. The modifier being a substance which facilitates the reduction of extreme anisotropic properties associated with body-centered-tetragonal tin based lead-free solder. The addition of the nucleation modifiers to the solder alloy does not materially effect the solder composition's melting point. As such, balls of solder with the nucleated composition freeze while other solder balls within the array remain in the melt. This effectively enables one substrate to be pinned to another substrate by one or more predetermined solder balls to secure the package while the remaining solder joints are in the liquid state.

Abstract translation: 简而言之，公开了一种新颖的材料方法，其中将一种或多种成核改性剂以痕量添加到无铅富锡焊料合金中以产生具有降低或抑制的过冷却温度特性的焊料组合物。 该改性剂是有助于减少与体心四方锡锡基无铅焊料相关的极端各向异性的物质。 将成核改性剂添加到焊料合金中不会实质上影响焊料组合物的熔点。 因此，具有成核组合物的焊料球冻结，而阵列内的其它焊球保持在熔体中。 这有效地使一个基板通过一个或多个预定的焊球被固定到另一个基板，以固定封装，而剩余的焊点处于液态。

公开(公告)号：US20090236725A1

公开(公告)日：2009-09-24

申请号：US12226764

申请日：2007-04-26

Applicant: Naohiko Hirano ,  Yoshitsugu Sakamoto ,  Tomomi Okumura ,  Kaichi Tsuruta ,  Minoru Ueshima ,  Takashi Ishii

Inventor： Naohiko Hirano ,  Yoshitsugu Sakamoto ,  Tomomi Okumura ,  Kaichi Tsuruta ,  Minoru Ueshima ,  Takashi Ishii

IPC: H01L23/488 ,  B23K35/24

CPC classification number: H05K3/3478 ,  B23K35/262 ,  B23K35/40 ,  H01L23/492 ,  H01L23/49866 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29211 ,  H01L2224/29355 ,  H01L2224/29499 ,  H01L2224/29582 ,  H01L2224/29611 ,  H01L2224/29694 ,  H01L2224/29695 ,  H01L2224/32225 ,  H01L2224/83101 ,  H01L2224/83455 ,  H01L2224/83801 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/15747 ,  H05K2201/0215 ,  H05K2201/2036 ,  H05K2203/0415 ,  H01L2924/00 ,  H01L2924/01028 ,  H01L2924/01026 ,  H01L2924/01049 ,  H01L2924/01083 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2224/13111 ,  H01L2224/13109 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929

Abstract: An electronic component having a semiconductor element bonded to a substrate with solder has a decreased bonding strength if there is not a suitable clearance between the semiconductor element and the substrate. Therefore, a solder preform having high melting point metal particles dispersed in solder has been used in the manufacture of electronic components. However, when an electronic component was manufactured using a conventional solder preform, there were cases in which the semiconductor element leaned or the bonding strength was not adequate.A solder preform according to the present invention has a variation in the size of high melting point metal particles which is at most 20 micrometers when the metal particle diameter is 50 micrometers, and an alloy layer of the high melting point metal particles and the main component of solder is formed around the high melting point metal particles. In addition, no voids at all are present in the solder. An electronic component according to the present invention has a semiconductor element bonded to a substrate with the above-described solder preform and has excellent resistance to heat cycles.

Abstract translation: 如果半导体元件和基板之间没有合适的间隙，则具有用焊料与基板结合的半导体元件的电子部件的接合强度降低。 因此，在电子部件的制造中已经使用了分散在焊料中的高熔点金属粒子的焊料预成型体。 然而，当使用常规的焊料预制件制造电子部件时，存在半导体元件倾斜或接合强度不足的情况。 根据本发明的焊料预成型体在金属粒径为50微米时具有至多20微米的高熔点金属颗粒的尺寸变化，并且高熔点金属颗粒和主要组分的合金层 的焊料形成在高熔点金属颗粒周围。 另外，在焊料中也不存在空隙。 根据本发明的电子部件具有利用上述焊料预成型件与基板结合的半导体元件，并具有优异的耐热循环性。

公开(公告)号：US07592065B2

公开(公告)日：2009-09-22

申请号：US10777082

申请日：2004-02-13

Applicant: Takahiro Matsumoto ,  Toshiaki Yamada ,  Hirotaka Tsuruya

Inventor： Takahiro Matsumoto ,  Toshiaki Yamada ,  Hirotaka Tsuruya

IPC: B32B5/16 ,  H01B1/08 ,  H01B1/20 ,  C01G30/00 ,  C01G19/00

CPC classification number: H05K1/162 ,  B82Y30/00 ,  C01P2004/64 ,  C01P2006/12 ,  C01P2006/40 ,  C04B35/628 ,  C04B35/62821 ,  C04B2235/3293 ,  C09C1/00 ,  H01B1/08 ,  H01B3/006 ,  H01B3/02 ,  H01B3/10 ,  H01G4/206 ,  H05K2201/0215 ,  H05K2201/0224 ,  H05K2201/0257 ,  Y10T428/268 ,  Y10T428/2991 ,  Y10T428/2993 ,  Y10T428/2998

Abstract: There are disclosed insulated ultrafine powder comprising electroconductive ultrafine powder which is in the form of sphere, spheroid or acicular each having a minor axis in the range of 1 to 100 nm and an insulating film applied thereto; a process for producing the same which is capable of covering the surfaces of the insulated ultrafine powder with the insulating film having a thickness in the range of 0.3 to 100 nm without causing any clearance or vacancy; and a resin composite material which uses the same. A high dielectric constant of the material is assured by adding a small amount of insulated ultrafine powder wherein an insulating film is applied to the electroconductive ultrafine powder, while maintaining the processability and moldability that are the characteristics inherent in a resin material.

Abstract translation: 公开了包含导电性超细粉末的绝缘超细粉末，其为球状，球状或针状，各具有1〜100nm的短轴和施加于其上的绝缘膜; 其制造方法能够利用厚度在0.3〜100nm范围内的绝缘膜覆盖绝缘超细粉末的表面，而不会产生任何间隙或空位; 和使用该树脂复合材料的树脂复合材料。 通过在保持作为树脂材料中固有的特性的加工性和成型性的同时，通过添加少量绝缘超细粉末来确保材料的高介电常数，其中绝缘膜被施加到导电超细粉末。

公开(公告)号：US20090190061A1

公开(公告)日：2009-07-30

申请号：US12343183

申请日：2008-12-23

Applicant: Gwan-Hyoung Lee ,  Young-Bee Chu ,  Sang-Hee Lee ,  Jeong-Seok Oh ,  Young-Soo Kim ,  Wal-Hee Kim

Inventor： Gwan-Hyoung Lee ,  Young-Bee Chu ,  Sang-Hee Lee ,  Jeong-Seok Oh ,  Young-Soo Kim ,  Wal-Hee Kim

IPC: F21V21/00 ,  G02F1/1333

CPC classification number: H05K1/0209 ,  H05K3/0061 ,  H05K2201/0209 ,  H05K2201/0215 ,  H05K2201/09781 ,  H05K2201/10106

Abstract: A printed circuit board (PCB) includes a base substrate, an electrical wiring, a dummy pad and a thermally conductive adhesion member. The base substrate includes a light-emitting diode (LED) mounted on a first surface of the base substrate. The electrical wiring is electrically connected to the LED. The dummy pad is formed on the first surface to be connected to the electrical wiring. The thermally conductive adhesion member is attached to a second surface of the base substrate. Therefore, superior heat radiation may be obtained, thereby reducing or preventing damage to the LED and the LCD device using the LED by radiating the heat from the LED used as a light source.

Abstract translation: 印刷电路板（PCB）包括基底基板，电线，虚拟焊盘和导热粘接部件。 基底基板包括安装在基底基板的第一表面上的发光二极管（LED）。 电线电连接到LED。 虚拟焊盘形成在要连接到电线的第一表面上。 导热粘合构件附接到基底基板的第二表面。 因此，可以获得优异的热辐射，从而通过辐射来自用作光源的LED的热量来减少或防止对使用LED的LED和LCD装置的损坏。