公开(公告)号：US20090050359A1

公开(公告)日：2009-02-26

申请号：US12229422

申请日：2008-08-21

Applicant: Wen-Hung Hu ,  Wen-Yuan Chi

Inventor： Wen-Hung Hu ,  Wen-Yuan Chi

IPC: H05K1/02 ,  H05K3/46

CPC classification number: H05K1/111 ,  H05K1/113 ,  H05K3/108 ,  H05K3/243 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2201/09781 ,  Y02P70/611 ,  Y10T29/49147

Abstract: A circuit board having an electrically connecting structure and a method for fabricating the same are provided. A circuit board body having inner-layer circuits is provided. A circuit layer is formed on at least an outermost surface of circuit board body, and including electrically connecting pads and circuits. The electrically connecting pads are partially electrically connected to the circuits, and are partially electrically connected to the inner-layer circuits via conductive vias. An insulating protective layer is disposed on the circuit board body and is formed with openings therein for exposing the electrically connecting pads. Conductive posts are formed on the electrically connecting pads. Standalone metal pads are formed on the insulating protective layer but are not used for electrical connection. The conductive posts and electrically connecting pads are absent from the insulating protective layer beneath the standalone metal pads, such that circuits can be formed under the insulating protective layer.

Abstract translation: 提供具有电连接结构的电路板及其制造方法。 提供具有内层电路的电路板主体。 电路层形成在电路板主体的至少最外表面上，并且包括电连接焊盘和电路。 电连接焊盘部分地电连接到电路，并且经由导电通孔部分地电连接到内层电路。 绝缘保护层设置在电路板主体上，并在其中形成有用于暴露电连接焊盘的开口。 导电柱形成在电连接焊盘上。 独立的金属焊盘形成在绝缘保护层上，但不用于电连接。 在独立的金属焊盘之下的绝缘保护层中不存在导电柱和电连接焊盘，使得电路可以形成在绝缘保护层下面。

公开(公告)号：US20090026462A1

公开(公告)日：2009-01-29

申请号：US12170783

申请日：2008-07-10

Applicant: Takafumi HASHIGUCHI

Inventor： Takafumi HASHIGUCHI

IPC: H01L29/04 ,  H01L21/84

CPC classification number: H05K3/3452 ,  H05K1/112 ,  H05K3/323 ,  H05K2201/0191 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/09709 ,  H05K2203/0577 ,  H05K2203/0588

Abstract: A wiring substrate includes a plurality of lines provided on the substrate, and a plurality of mounting terminals each for respective one of the plurality of lines, the plurality of mounting terminals being arranged in several rows in a staggered pattern, wherein the mounting terminal includes a first conductive film formed in the same layer as the lines, an insulating film covering the lines and the first conductive film, the insulating film having an opening above the first conductive film, and an upper layer conducive film electrically connected to the first conductive film through the opening, and wherein the insulating film includes a thick film portion located on the outside of the area where the plurality of mounting terminals are arranged in several rows in the staggered pattern, and a thin film portion located in the area adjacent to the opening in the row direction of the staggered pattern with a thickness thinner than the thick film portion.

Abstract translation: 布线基板包括设置在基板上的多条线和多条安装端子，各安装端子分别用于多条线路中的一条线路，多个安装端子以交错图案布置成数行，其中安装端子包括 形成在与该线相同的层中的第一导电膜，覆盖线和第一导电膜的绝缘膜，在第一导电膜上方具有开口的绝缘膜，以及与第一导电膜通过电连接的上层导电膜 并且其中所述绝缘膜包括位于所述多个安装端子以交错图案布置成多行的区域的外侧的厚膜部分，以及位于与所述开口相邻的区域中的薄膜部分 交错图案的行方向的厚度比厚膜部分薄。

公开(公告)号：US20080257595A1

公开(公告)日：2008-10-23

申请号：US12081423

申请日：2008-04-16

Applicant: Wen-Hung Hu

Inventor： Wen-Hung Hu

IPC: H01R12/04 ,  H05K3/10

CPC classification number: H05K3/4007 ,  H01L23/49816 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05111 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2924/00014 ,  H01L2924/14 ,  H01R12/57 ,  H05K3/06 ,  H05K3/243 ,  H05K3/28 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2201/09745 ,  H05K2203/0353 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2924/01024 ,  H01L2924/01082 ,  H01L2924/01022 ,  H01L2924/01079 ,  H01L2924/01046

Abstract: The present invention relates to a packaging substrate and a method for manufacturing the same. The packaging substrate includes: a substrate body, having a plurality of conductive pads on the surface thereof, wherein the top surfaces of the conductive pads have a concave each; a solder mask, disposed on the surface of the substrate body and having a plurality of openings to correspondingly expose the concaves of the conductive pads each; and a plurality of metal bumps, disposed correspondingly in the openings of the solder mask and over the concaves of the conductive pads. The present invention increases the joint surface area between the metal bumps and the conductive pads so as to inhibit the joint crack and improve the reliability of the conductive structure of the packaging substrate.

Abstract translation: 本发明涉及一种包装基板及其制造方法。 封装基板包括：基板主体，其表面上具有多个导电焊盘，其中导电焊盘的顶表面各具有凹面; 焊接掩模，设置在基板主体的表面上并且具有多个开口以相应地暴露每个导电焊盘的凹部; 以及多个金属凸块，相应地设置在焊料掩模的开口中并在导电焊盘的凹部之上。 本发明增加了金属凸块和导电焊盘之间的接合表面积，从而抑制接头裂纹，提高了封装基板的导电结构的可靠性。

公开(公告)号：US07427557B2

公开(公告)日：2008-09-23

申请号：US11075474

申请日：2005-03-09

Applicant: Glenn A. Rinne ,  J. Daniel Mis

Inventor： Glenn A. Rinne ,  J. Daniel Mis

IPC: H01L21/44

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05178 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05557 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/062 ,  H05K3/243 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2203/054 ,  H05K2203/0723 ,  H01L2924/00014 ,  H01L2924/013

Abstract: Forming an electronic structure may include forming a seed layer on a substrate, and forming a mask on the seed layer. The mask may include an aperture therein exposing a portion of the seed layer, and a barrier layer may be formed on the exposed portion of the seed layer. A bump may be formed on the barrier layer, and the mask may be removed. In addition, portions of the seed layer may be selectively removed using the barrier layer as an etch mask.

Abstract translation: 形成电子结构可以包括在基底上形成种子层，并在种子层上形成掩模。 掩模可以包括其中露出种子层的一部分的孔，并且阻挡层可以形成在种子层的暴露部分上。 可以在阻挡层上形成凸起，并且可以去除掩模。 此外，可以使用阻挡层作为蚀刻掩模来选择性地去除种子层的部分。

公开(公告)号：US07420644B2

公开(公告)日：2008-09-02

申请号：US10876615

申请日：2004-06-28

Applicant: Kwang Sub Park

Inventor： Kwang Sub Park

IPC: G02F1/1345

CPC classification number: G02F1/13452 ,  H05K1/117 ,  H05K3/323 ,  H05K3/361 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/0979

Abstract: A liquid crystal display device includes a lower pad electrode connected to a signal line of a liquid crystal display panel, one or more insulating layers formed on the lower pad electrode, a plurality of minute holes passing through the one or more insulating layers to expose a portion of the lower pad electrode, one or more main contact holes passing through the one or more insulating layers to expose another portion of the lower pad electrode, and an upper pad electrode electrically connected to the lower pad electrode via the minute holes and the one or more main contact holes. An area of the one or more main contact holes is larger than an area of each of the plurality of minute holes.

Abstract translation: 液晶显示装置包括连接到液晶显示面板的信号线的下焊盘电极，形成在下焊盘电极上的一个或多个绝缘层，穿过所述一个或多个绝缘层的多个微孔暴露于 所述下焊盘电极的一部分，穿过所述一个或多个绝缘层的一个或多个主接触孔以暴露所述下焊盘电极的另一部分，以及通过所述微孔电连接到所述下焊盘电极的上焊盘电极， 或更多的主接触孔。 一个以上的主接触孔的面积大于多个微孔的面积。

公开(公告)号：US07350298B2

公开(公告)日：2008-04-01

申请号：US11467629

申请日：2006-08-28

Applicant: Shih-Ping Hsu ,  Sao-Hsia Tang ,  Ying-Tung Wang ,  Wen Hung Hu ,  Chao Wen Shih

Inventor： Shih-Ping Hsu ,  Sao-Hsia Tang ,  Ying-Tung Wang ,  Wen Hung Hu ,  Chao Wen Shih

IPC: H01K3/10 ,  H05K3/02 ,  H05K3/34

CPC classification number: H05K3/3484 ,  H05K1/112 ,  H05K3/1216 ,  H05K3/243 ,  H05K3/3473 ,  H05K2201/0391 ,  H05K2201/09436 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2203/054 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method for fabricating a circuit board having a conductive structure is disclosed. The method includes: forming first and second insulating protective layers respectively on first and second surfaces of a circuit board; forming a conductive layer on the first insulating protective layer and the openings; forming first and second resist layers on the conductive layer and the second insulating protective layer respectively; forming first electrically connecting structures by electroplating on the exposed conductive layer over a plurality of first and second electrically connecting pads in openings of the first resist layer; removing the first and the second resist layers and the conductive layer covered by the first resist layer; and forming second electrically connecting structures by stencil printing on the conductive layer over the second electrically connecting pads on the first surface and on a plurality of third electrically connecting pads of the second surface of the circuit board.

Abstract translation: 公开了一种制造具有导电结构的电路板的方法。 该方法包括：分别在电路板的第一和第二表面上形成第一和第二绝缘保护层; 在所述第一绝缘保护层和所述开口上形成导电层; 分别在导电层和第二绝缘保护层上形成第一和第二抗蚀剂层; 通过在所述第一抗蚀剂层的开口中的多个第一和第二电连接焊盘上的暴露的导电层上电镀来形成第一电连接结构; 去除由第一抗蚀剂层覆盖的第一和第二抗蚀剂层和导电层; 以及通过在第一表面上的第二电连接焊盘和电路板的第二表面的多个第三电连接焊盘上的导电层上的模版印刷形成第二电连接结构。

公开(公告)号：US07335608B2

公开(公告)日：2008-02-26

申请号：US10948386

申请日：2004-09-22

Applicant: Ravindra V. Tanikella

Inventor： Ravindra V. Tanikella

IPC: H01L21/31 ,  H01L21/302

CPC classification number: H01L23/49894 ,  C08F283/04 ,  C08G73/121 ,  C08K3/36 ,  C08K9/10 ,  C08K2201/011 ,  C08L79/08 ,  C08L2666/66 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/293 ,  H01L23/295 ,  H01L23/296 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49866 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/15763 ,  H01L2924/15787 ,  H01L2924/15791 ,  H01L2924/18161 ,  H01L2924/351 ,  H05K1/112 ,  H05K3/28 ,  H05K3/421 ,  H05K3/422 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/0158 ,  H05K2201/09436 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09827 ,  H05K2203/1163 ,  H05K2203/121 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts). In one embodiment, the solder resist opening walls have a wettable layer generated through laser assisted seeding so that there is no gap between the solder resist opening walls and no underfill in the solder resist opening.

公开(公告)号：US20070114673A1

公开(公告)日：2007-05-24

申请号：US11655238

申请日：2007-01-19

Applicant: Kei Murayama ,  Masahiro Sunohara

Inventor： Kei Murayama ,  Masahiro Sunohara

IPC: H01L23/48

CPC classification number: H01L23/49827 ,  H01L23/562 ,  H01L24/81 ,  H01L2224/16 ,  H01L2224/81206 ,  H01L2224/81801 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H05K1/113 ,  H05K3/328 ,  H05K2201/09436 ,  H05K2201/09781 ,  H05K2201/0979 ,  H05K2201/10674 ,  H05K2203/0285 ,  H01L2924/00

Abstract: In a wiring substrate of the present invention in which a bump of an electronic parts is bonded to a connection pad of a wiring pattern provided on an insulating film by an ultrasonic flip-chip packaging, a via hole into which a via post acting as a strut to support the connection pad upon the ultrasonic flip-chip packaging is filled is arranged in the insulating film under the connection pad.

公开(公告)号：US20070024794A1

公开(公告)日：2007-02-01

申请号：US11542298

申请日：2006-10-02

Applicant: Dong-Gyu Kim

Inventor： Dong-Gyu Kim

IPC: G02F1/1345

CPC classification number: G02F1/13458 ,  G02F1/13452 ,  G02F2001/133357 ,  G02F2001/133388 ,  H01L2224/16225 ,  H01L2924/00014 ,  H05K1/114 ,  H05K1/117 ,  H05K3/323 ,  H05K3/361 ,  H05K2201/09436 ,  H01L2224/0401

Abstract: Disclosed are a liquid crystal display (LCD) and a method for manufacturing the same, in which connection stability is improved when connecting a COG, A COF, or an FPC to a driving circuit. A substrate of the LCD has a display region and a non-display region at a peripheral area thereof. Terminals are provided to electrically connect an external circuit and a circuit of the display region and the non-display region. A flat protective layer is formed on the terminals. A plurality of pads are respectively formed of a first contact region and a flat second contact region, and each of the pads contacts a corresponding terminal, which is formed through a pad contact hold formed on the protective layer, at the first contact region, and each of the pads is electrically connected through an anisotropic conductive resin to a terminal of the external circuit by a pressing process at the flat second contact region.

公开(公告)号：US20060252249A1

公开(公告)日：2006-11-09

申请号：US11429766

申请日：2006-05-08

Applicant: Shih-Ping Hsu ,  Sao-Hsia Tang ,  Ying-Tung Wang ,  Wen-Hung Hu ,  Chao-Wen Shih

Inventor： Shih-Ping Hsu ,  Sao-Hsia Tang ,  Ying-Tung Wang ,  Wen-Hung Hu ,  Chao-Wen Shih

IPC: H01L21/44

CPC classification number: H05K3/243 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H05K1/111 ,  H05K3/062 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/09436 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09745 ,  H05K2201/10734 ,  H05K2203/054 ,  H05K2203/0723 ,  Y02P70/611 ,  H01L2924/00014

Abstract: A solder ball pad surface finish structure of a circuit board and a method for fabricating the same are proposed. An insulative protecting layer with a plurality of openings is formed on a circuit board to expose solder ball pads on the circuit board. A conductive layer is formed on the insulative protecting layer and in the openings, and a resist layer is also formed thereon. A plurality of openings are formed and defined in the resist layer corresponding to the solder ball pads. The area of openings of resist layer can be larger or smaller than the area of the openings of insulative protecting layer, and the resist layer is hung above the solder ball pads. A metal layer is formed on the conductive layer and in the openings of resist layer by electroplating and an adhesive layer is formed successively. Then, the resist layer and the conductive layer underneath the resist layer are removed. Afterwards, the adhesive layer is further processed by re-flow process.

Abstract translation: 提出了一种电路板的焊球焊盘表面光洁度结构及其制造方法。 在电路板上形成具有多个开口的绝缘保护层，以露出电路板上的焊球垫。 在绝缘保护层和开口中形成导电层，并且还在其上形成抗蚀剂层。 在对应于焊球垫的抗蚀剂层中形成并限定多个开口。 抗蚀剂层的开口面积可以大于或小于绝缘保护层的开口面积，并且抗蚀剂层悬挂在焊球垫上方。 通过电镀在导电层和抗蚀剂层的开口中形成金属层，并依次形成粘合剂层。 然后，去除抗蚀剂层和抗蚀剂层下面的导电层。 然后，通过再流程进一步处理粘合剂层。