公开(公告)号：US08183465B2

公开(公告)日：2012-05-22

申请号：US12575504

申请日：2009-10-08

Applicant: Shinya Suzuki ,  Kenichi Saita ,  Shinya Miyamoto ,  Shinji Yuri

Inventor： Shinya Suzuki ,  Kenichi Saita ,  Shinya Miyamoto ,  Shinji Yuri

IPC: H05K1/16

CPC classification number: H05K1/185 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15312 ,  H05K1/0231 ,  H05K1/113 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/068 ,  H05K2201/096 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A component built-in wiring substrate (10) which includes: a core substrate (11); a plate-shaped component (101); a resin filling portion (92); and a wiring stacking portion (31), wherein, when viewed from the core principal surface (12) side, the projected area of the mounting area (32) is larger than the projected area of the plate-shaped component (101) and the resin filling portion, and the plate-shaped component and the resin filling portion are positioned directly below the mounting area (23), and wherein a value of the coefficient of thermal expansion (CTE α2) for a temperature range that is equal to or higher than the glass transition temperature of the resin filling portion is set to be larger than a value of the coefficient of thermal expansion of the plate-shaped component and smaller than a value of the coefficient of thermal expansion of the core substrate for the subject temperature range.

Abstract translation: 一种组件内置布线基板（10），包括：芯基板（11）; 板状部件（101）; 树脂填充部分（92）; 以及布线堆叠部（31），其中，当从所述芯主表面（12）侧观察时，所述安装区域（32）的所述投影面积大于所述板状部件（101）的投影面积，并且 树脂填充部分，并且板状部件和树脂填充部分位于安装区域（23）的正下方，并且其中等于或等于更高的温度范围的热膨胀系数（CTEα2）的值 将树脂填充部的玻璃化转变温度设定为大于板状部件的热膨胀系数的值，并且小于本体温度范围内的芯基板的热膨胀系数的值 。

公开(公告)号：US08072732B2

公开(公告)日：2011-12-06

申请号：US12100527

申请日：2008-04-10

Applicant: Motohiko Sato ,  Kenji Murakami ,  Jun Otsuka ,  Manabu Sato ,  Masahiko Okuyama ,  Kozo Yamazaki

Inventor： Motohiko Sato ,  Kenji Murakami ,  Jun Otsuka ,  Manabu Sato ,  Masahiko Okuyama ,  Kozo Yamazaki

IPC: H01G4/005

CPC classification number: H05K1/0231 ,  H01G4/232 ,  H01G4/30 ,  H01G4/33 ,  H01L23/50 ,  H01L23/642 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01025 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10712 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A capacitor is provided having a tough surface portion which prevents cracking that tends to occur when the capacitor is built-in or surface-mounted on a wiring board. A ceramic sintered body of the capacitor includes a capacitor forming layer portion, a cover layer portion and an interlayer portion. The capacitor forming layer portion has a laminated structure wherein ceramic dielectric layers and inner electrodes connected to a peripheral portion of capacitor via conductors, are alternately laminated. The cover layer portion is exposed at a surface portion of the ceramic body and has a laminated structure wherein ceramic dielectric layers and dummy electrodes not connected to the capacitor via conductors, are alternately laminated.

Abstract translation: 提供一种电容器，其具有坚韧的表面部分，其防止当电容器内置或表面安装在布线板上时容易发生的开裂。 电容器的陶瓷烧结体包括电容器形成层部分，覆盖层部分和中间层部分。 电容器形成层部分具有层叠结构，其中陶瓷电介质层和连接到电容器通孔导体的周边部分的内部电极交替层叠。 覆盖层部分在陶瓷体的表面部分露出，并且具有层叠结构，其中不连接到电容器通孔导体的陶瓷电介质层和虚拟电极交替层叠。

公开(公告)号：US07932471B2

公开(公告)日：2011-04-26

申请号：US11498785

申请日：2006-08-04

Applicant: Hiroshi Yamamoto ,  Toshitake Seki ,  Shinji Yuri ,  Masaki Muramatsu ,  Motohiko Sato ,  Kazuhiro Hayashi ,  Jun Otsuka ,  Manabu Sato

Inventor： Hiroshi Yamamoto ,  Toshitake Seki ,  Shinji Yuri ,  Masaki Muramatsu ,  Motohiko Sato ,  Kazuhiro Hayashi ,  Jun Otsuka ,  Manabu Sato

IPC: H05K1/16

CPC classification number: H01G4/232 ,  H01G4/30 ,  H01L23/49822 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/096 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/05599

Abstract: A capacitor comprising: a capacitor body including a plurality of laminated dielectric layers, a plurality of inner electrode layers which are respectively disposed between mutually adjacent ones of the dielectric layers, a first main surface located in a laminated direction of the dielectric layers, and a second main surface opposite to the first main surface; a first outer electrode formed on the first main surface of the capacitor body and electrically connected to the inner electrode layers; a second outer electrode formed on the second main surface of the capacitor body and electrically connected to the inner electrode layers; a first dummy electrode formed on the first main surface of the capacitor body; and a second dummy electrode formed on the second main surface of the capacitor body.

Abstract translation: 一种电容器，包括：电容器主体，包括多个叠层电介质层，多个内部电极层，分别设置在相互相邻的电介质层之间，第一主表面位于电介质层的层叠方向上， 第二主表面与第一主表面相对; 第一外电极，形成在所述电容器主体的所述第一主表面上并电连接到所述内电极层; 形成在所述电容器主体的所述第二主表面上并与内部电极层电连接的第二外部电极; 形成在所述电容器主体的所述第一主表面上的第一虚拟电极; 以及形成在电容器主体的第二主表面上的第二虚拟电极。

公开(公告)号：US20100163168A1

公开(公告)日：2010-07-01

申请号：US12647791

申请日：2009-12-28

Applicant: Kenichi SAITA ,  Shinji Yuri ,  Shinya Miyamoto ,  Shinya Suzuki

Inventor： Kenichi SAITA ,  Shinji Yuri ,  Shinya Miyamoto ,  Shinya Suzuki

IPC: B32B38/10 ,  B32B37/00

CPC classification number: H05K1/185 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/1461 ,  H05K1/0231 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method for manufacturing a wiring board includes a core substrate preparation step, a component preparation step, an accommodation step, a resin layer formation step, a fixing step, an insulation layer and a surface modification step. In the accommodation step, a component is held in an accommodation hole of a core substrate. In the resin layer formation step, a gap between an inner wall surface of the accommodation hole and a side surface of the component is filled with a resin layer. In the fixing step, the resin layer is hardened. In the insulation layer formation step, a resin insulation layer is formed on a second major surface and a second component major surface. In the surface modification step, a surface of the resin layer is modified, after the fixing step but before the insulation layer formation step.

Abstract translation: 制造布线板的方法包括芯基板制备步骤，组分制备步骤，调节步骤，树脂层形成步骤，定影步骤，绝缘层和表面改性步骤。 在接合步骤中，将部件保持在芯基板的容纳孔中。 在树脂层形成工序中，将填充孔的内壁面与部件的侧面之间的间隙填充树脂层。 在定影步骤中，树脂层硬化。 在绝缘层形成步骤中，在第二主表面和第二组分主表面上形成树脂绝缘层。 在表面改性工序中，树脂层的表面在固定步骤之后，但在绝缘层形成步骤之前被改变。

公开(公告)号：US20100139090A1

公开(公告)日：2010-06-10

申请号：US12706695

申请日：2010-02-16

Applicant: Masaki MURAMATSU ,  Shinji YURI ,  Makoto ORIGUCHI ,  Kazuhiro URASHIMA

Inventor： Masaki MURAMATSU ,  Shinji YURI ,  Makoto ORIGUCHI ,  Kazuhiro URASHIMA

IPC: H05K3/10

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01055 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/351 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/142 ,  H05K1/162 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/096 ,  H05K2201/10674 ,  H05K2201/10712 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A wiring board comprising: a core board including a core body and a ceramic sub-core which is accommodated in a sub-core accommodation space that is a through-hole that communicates with major surfaces of the core body or a recess having an opening in a first major surface of the core body; and wiring laminates each formed by resin insulating layers and conductor layers laminated on each of major surfaces of the core board, wherein: a groove-filling portion which fills a gap between the core body and the ceramic sub-core is integral with a lowest resin insulating layer of the first-major-surface-side wiring laminate; and via conductors that are connected to respective conductor patterns formed on a first major surface of the ceramic sub-core penetrate through the lowest resin insulating layer.

Abstract translation: 一种布线板，包括：芯板，其包括芯体和陶瓷子芯，所述芯体容纳在与所述芯体的主表面连通的通孔的子芯容纳空间中，或者具有开口的凹部 核心体的第一个主要表面; 以及由层叠在芯板的各主表面上的树脂绝缘层和导体层形成的布线层叠体，其中，填充芯体与陶瓷副芯之间的间隙的沟槽填充部与最低树脂 第一主表面侧布线层叠体的绝缘层; 并且连接到形成在陶瓷子芯的第一主表面上的相应导体图案的通孔导体穿透最低树脂绝缘层。

公开(公告)号：US07704548B2

公开(公告)日：2010-04-27

申请号：US11739798

申请日：2007-04-25

Applicant: Tadahiko Kawabe ,  Masao Kuroda ,  Yasuhiro Sugimoto ,  Hajime Saiki ,  Shinji Yuri ,  Makoto Origuchi

Inventor： Tadahiko Kawabe ,  Masao Kuroda ,  Yasuhiro Sugimoto ,  Hajime Saiki ,  Shinji Yuri ,  Makoto Origuchi

IPC: B05D5/12 ,  H01B13/00

CPC classification number: H05K1/185 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15311 ,  H05K1/0231 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/10674 ,  H05K2201/10712 ,  Y10T29/49155 ,  H01L2224/05599

Abstract: A method for manufacturing a wiring board which can simplify a manufacturing step. In a preparation step, a core board and an electronic component are prepared. In an insulating layer formation and fixing step, after accommodating the electronic component in an accommodation hole, a lowermost resin insulating layer is formed, and a gap between the electronic component and the core board is filled with a part of the lowermost resin insulating layer so as to fix the electronic component to the core board. In an opening portion formation step, a portion of the lowermost resin insulating layer located directly above the gap between the electronic component and the core board is removed so as to form an opening portion exposing a part of a core board main surface side conductor and a component main surface side electrode. In a main surface side connecting conductor formation step, a main surface side connecting conductor is formed in the opening portion so as to connect the core board main surface side conductor to the component main surface side electrode.

Abstract translation: 一种制造布线板的方法，其可以简化制造步骤。 在准备步骤中，制备核心板和电子部件。 在绝缘层形成和定影步骤中，在将电子部件容纳在容纳孔中之后，形成最下层的树脂绝缘层，并且用最下层的树脂绝缘层的一部分填充电子部件与芯板之间的间隙 以将电子部件固定到核心板。 在开口部形成工序中，除去位于电子部件与芯板之间的间隙正上方的最下层树脂绝缘层的一部分，以形成露出芯板主面侧导体和 部件主表面侧电极。 在主表面侧连接导体形成步骤中，在开口部分形成主表面侧连接导体，以将芯板主表面侧导体连接到部件主表面侧电极。

公开(公告)号：US07456078B2

公开(公告)日：2008-11-25

申请号：US11393910

申请日：2006-03-31

Applicant: Kazuaki Kurihara ,  Takeshi Shioga ,  John David Baniecki ,  Masatoshi Ishii

Inventor： Kazuaki Kurihara ,  Takeshi Shioga ,  John David Baniecki ,  Masatoshi Ishii

IPC: H01L21/20

CPC classification number: H01L23/5223 ,  H01G4/33 ,  H01L23/3114 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L28/55 ,  H01L28/65 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/1147 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/14 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/30105 ,  H01L2924/30107 ,  H05K1/0231 ,  H05K1/162 ,  H05K1/185 ,  H05K2201/0179 ,  H05K2201/09481 ,  H05K2201/10712 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: The thin-film capacitor comprises a capacitor part 20 formed over a base substrate 10 and including a first capacitor electrode 14, a capacitor dielectric film 16 formed over the first capacitor electrode 14, and a second capacitor electrode 18 formed over the capacitor dielectric film 16; leading-out electrodes 26a, 26b lead from the first capacitor electrode 14 or the second capacitor electrode 18 and formed of a conducting barrier film which prevents the diffusion of hydrogen or water; and outside connection electrodes 34a, 34b for connecting to outside and connected to the leading-out electrodes 26a, 26b.

Abstract translation: 薄膜电容器包括形成在基底基板10上并包括第一电容器电极14，形成在第一电容器电极14上的电容器电介质膜16的电容器部分20和形成在电容器电介质膜16上的第二电容器电极18 ; 引出电极26a，26b从第一电容器电极14或第二电容器电极18引出，并由阻止氢或水扩散的导电阻挡膜形成; 以及用于连接到外部并连接到引出电极26a，26b的外部连接电极34a，34b。

公开(公告)号：US07345246B2

公开(公告)日：2008-03-18

申请号：US11350285

申请日：2006-02-09

Applicant: Masaki Muramatsu ,  Shinji Yuri ,  Kazuhiro Urashima ,  Hiroshi Yamamoto ,  Toshitake Seki ,  Motohiko Sato

Inventor： Masaki Muramatsu ,  Shinji Yuri ,  Kazuhiro Urashima ,  Hiroshi Yamamoto ,  Toshitake Seki ,  Motohiko Sato

IPC: H05K1/16

CPC classification number: H01G2/06 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/10 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: An intermediate board has a board core formed by a main core body and a sub-core portion. The main core body has a plate-like shape and includes an open sub-core housing portion in which the sub-core portion is housed. A first terminal array of the board core has an area that overlaps an orthogonal projection of the sub-core portion. The latter incorporates a laminated ceramic capacitor formed by first and second conductor layers with a ceramic (dielectric) layer therebetween. The first layer is connected to first and second side terminals of a first type while the second layer is connected to first and second side terminals of a second type. The housing portion has an inner edge which, in cross section, is of a quadrate shape, and a radius portion is formed at each corner having a dimension of between 0.1 and 2 mm.

Abstract translation: 中间板具有由主芯体和副芯部形成的板芯。 主芯体具有板状形状，并且包括其中容纳有副芯部的开放子芯容纳部。 板芯的第一端子阵列具有与子芯部的正交突起重叠的区域。 后者包括由其间具有陶瓷（电介质）层的第一和第二导体层形成的层叠陶瓷电容器。 第一层连接到第一类型的第一和第二侧端子，而第二层连接到第二类型的第一和第二侧端子。 壳体部分具有横截面为正方形的内边缘，并且在每个角部处形成具有0.1至2mm的尺寸的半径部分。

公开(公告)号：US20080043400A1

公开(公告)日：2008-02-21

申请号：US11837059

申请日：2007-08-10

Applicant: Hidetaka Fukudome ,  Masashi Nishimura ,  Masaaki Taniguchi ,  Yoshio Kawaguchi

Inventor： Hidetaka Fukudome ,  Masashi Nishimura ,  Masaaki Taniguchi ,  Yoshio Kawaguchi

IPC: H01G4/30 ,  H05K1/14

CPC classification number: H05K1/0231 ,  H01G4/2325 ,  H01G4/30 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/642 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15313 ,  H01L2924/3011 ,  H05K1/185 ,  H05K2201/10712 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A monolithic capacitor includes a laminate of ceramic layers, the laminate having first and second surfaces, at least one pair of first and second internal electrodes, first and second external electrodes disposed on the first surface, third and fourth external electrodes disposed on the second surface, a first via conductor that electrically connects the first external electrode to the first internal electrode and to the third external electrode and that contains a metal oxide, and a second via conductor that electrically connects the second external electrode to the second internal electrode and to the fourth external electrode and that contains a metal oxide, wherein, in each of the first and second via conductors, the metal oxide content at an end on the second surface side is higher than the metal oxide content at a center or at an end on the first surface side.

Abstract translation: 单片电容器包括陶瓷层的层叠体，层叠体具有第一表面和第二表面，至少一对第一和第二内部电极，设置在第一表面上的第一和第二外部电极，设置在第二表面上的第三和第四外部电极 第一通孔导体，其将第一外部电极与第一内部电极和第三外部电极电连接并且包含金属氧化物;以及第二通路导体，其将第二外部电极与第二内部电极电连接， 第四外部电极，其含有金属氧化物，其中，在所述第一和第二导体导体的每一个中，所述第二表面侧的端部的金属氧化物含量高于所述第二和第二导体的中心或末端的金属氧化物含量 第一表面。

公开(公告)号：US20070121273A1

公开(公告)日：2007-05-31

申请号：US11601760

申请日：2006-11-20

Applicant: Hiroshi Yamamoto ,  Toshitake Seki ,  Yasuhiko Inui ,  Jun Otsuka ,  Manabu Sato

Inventor： Hiroshi Yamamoto ,  Toshitake Seki ,  Yasuhiko Inui ,  Jun Otsuka ,  Manabu Sato

IPC: H01G4/228

CPC classification number: H01G4/30 ,  H01G4/232 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/185 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/05599

Abstract: In order to provide a built-in capacitor type wiring board capable of preventing misalignment of the capacitor, a capacitor built-in type wiring board is provided which includes a core board; a multilayer portion disposed on at least one side of the core board and formed by a plurality of interlayer insulating layers; and a plurality of conductor layers alternately laminated on the core board. The capacitor is of a chip-like shape with first and second main surfaces and includes a dielectric layer; electrode layers laminated on the dielectric layer; and a hole portion opening at least at the second main surface. The capacitor is embedded in the interlayer insulating layers so that the second main surface faces the core board.

Abstract translation: 为了提供能够防止电容器未对准的内置电容器型布线板，提供了一种电容器内置型布线板，其包括芯板; 多层部分，设置在所述芯板的至少一侧上，并由多个层间绝缘层形成; 以及在芯板上交替层叠的多个导体层。 电容器是具有第一和第二主表面的芯片状形状并且包括电介质层; 层压在电介质层上的电极层; 以及至少在所述第二主表面处开口的孔部分。 电容器嵌入在层间绝缘层中，使得第二主表面面向芯板。