公开(公告)号：US08697534B2

公开(公告)日：2014-04-15

申请号：US13610936

申请日：2012-09-12

Applicant: Motohiko Sato ,  Kazuhiro Hayashi ,  Kenji Murakami ,  Motonobu Kurahashi ,  Yusuke Kaieda ,  Jun Otsuka ,  Manabu Sato

Inventor： Motohiko Sato ,  Kazuhiro Hayashi ,  Kenji Murakami ,  Motonobu Kurahashi ,  Yusuke Kaieda ,  Jun Otsuka ,  Manabu Sato

IPC: H01L21/20

CPC classification number: H05K1/0231 ,  H01G4/228 ,  H01G4/30 ,  H01G4/38 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10712 ,  H01L2924/00

Abstract: A wiring substrate in which a capacitor is provided, the capacitor comprising a capacitor body including a plurality of dielectric layers and internal electrode layers provided between the different dielectric layers, wherein said capacitor body has, in at least one side face of said capacitor body, recesses extending in a thickness direction of said capacitor body from at least one of a first principal face of said capacitor body and a second principal face positioned on the side opposite to the first principal face.

Abstract translation: 一种电容器，其具有电容器，所述电容器包括：电容器主体，包括多个电介质层和设置在所述不同电介质层之间的内部电极层，其中所述电容器本体在所述电容器主体的至少一个侧面中， 从所述电容器主体的第一主面和位于与所述第一主面相反的一侧的第二主面中的至少一个在所述电容器本体的厚度方向上延伸的凹部。

公开(公告)号：US20130074332A1

公开(公告)日：2013-03-28

申请号：US13626477

申请日：2012-09-25

Applicant: NGK SPARK PLUG CO., LTD.

Inventor： Kenji SUZUKI

IPC: H05K3/38 ,  H05K3/30

CPC classification number: H05K3/306 ,  H01L2224/16225 ,  H01L2924/1461 ,  H01L2924/1531 ,  H05K1/0218 ,  H05K1/0222 ,  H05K1/185 ,  H05K3/0094 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09981 ,  H05K2201/10712 ,  H05K2203/1394 ,  Y10T29/49133 ,  Y10T29/49135 ,  H01L2924/00

Abstract: A method of manufacturing a component-built-in wiring substrate which exhibits excellent reliability, through improvement of adhesion between a resin filler and a core substrate, is provided. In some embodiments the method comprises a core substrate preparation step for preparing a core substrate, an accommodation-hole forming step for forming an accommodation hole in the core substrate, and a through-hole forming step for forming through-holes. In a plating-layer forming step, a plating layer is formed on an inner wall surface of the accommodation hole and plating layers are formed on the inner wall surfaces of the through-holes, which become through-hole conductors each having a hollow. In an accommodation step, a component is accommodated in the accommodation hole. In a resin charging step, a resin filler is filled into a gap between component side-surfaces and the inner wall surface of the accommodation hole and into the hollows.

公开(公告)号：US20110018099A1

公开(公告)日：2011-01-27

申请号：US12933522

申请日：2009-03-24

Applicant: Masaki Muramatsu

Inventor： Masaki Muramatsu

IPC: H01L27/08

CPC classification number: H05K1/162 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/1461 ,  H01L2924/15311 ,  H05K1/02 ,  H05K1/0231 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09309 ,  H05K2201/096 ,  H05K2201/09763 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: An objective is to provide a component-incorporated wiring substrate capable of solving a problem caused by an increase in length of wiring lines that connect a component and a capacitor. A component-incorporated wiring substrate 10 includes a core substrate 11, a first capacitor 301, a wiring laminate portion 31, and a second capacitor 101. An accommodation hole portion 90 of the core substrate 11 accommodates the first capacitor 101 therein, and a component-mounting region 20 is set on a surface 39 of the wiring laminate portion 31. The second capacitor 101 has electrode layers 102, 103 and a dielectric layer 104. The second capacitor 101 is embedded in the wiring laminate portion 31 in such a state that first main surfaces 105, 107 and second main surfaces 106, 108 are in parallel with the surface 39 of the wiring laminate portion 31, and is disposed between the first capacitor 301 and the component-mounting region 20.

Abstract translation: 目的是提供一种能够解决由连接部件和电容器的布线的长度增加引起的问题的配有部件的布线基板。 构成部件的布线基板10具有芯基板11，第一电容器301，布线层叠部31和第二电容器101.芯基板11的容纳孔部90容纳第一电容器101， 安装区域20设置在布线层叠部分31的表面39上。第二电容器101具有电极层102,103和电介质层104.第二电容器101以这样的状态嵌入布线层叠部分31中 第一主表面105,107和第二主表面106,108与布线层压体部分31的表面39平行，并且设置在第一电容器301和部件安装区域20之间。

公开(公告)号：US20110007482A1

公开(公告)日：2011-01-13

申请号：US12821543

申请日：2010-06-23

Applicant: Rie Takada ,  Kenichiro Tsubone

Inventor： Rie Takada ,  Kenichiro Tsubone

IPC: H05K1/00

CPC classification number: H05K3/363 ,  H01L2224/16225 ,  H05K1/147 ,  H05K2201/0949 ,  H05K2201/10674 ,  H05K2201/10712

Abstract: A printed circuit board unit includes a printed circuit board including through holes arranged in a grid array on which an integrated circuit is mounted; and a flexible substrate provided on a back side of the printed circuit board, covering the through holes. First lands to which the integrated circuit is connected are formed on a front side of the printed circuit board. Second lands to which the flexible substrate is connected are formed on the back side of the printed circuit board. The first lands and the second lands are connected to first ends and second ends of the through holes, respectively. Third lands are formed on a front side of the flexible substrate so as to face the second lands of the printed circuit board. Fourth lands are formed on a back side of the flexible substrate. The fourth lands are electrically connected to the third lands.

Abstract translation: 印刷电路板单元包括印刷电路板，其包括布置在其上安装集成电路的栅格阵列中的通孔; 以及设置在印刷电路板的背侧的柔性基板，覆盖通孔。 在印刷电路板的前侧形成有连接有集成电路的第一焊盘。 在印刷电路板的背面形成有连接柔性基板的第二平台。 第一平台和第二平台分别连接到通孔的第一端和第二端。 第三平台形成在柔性基板的前侧，以面对印刷电路板的第二平台。 第四平台形成在柔性基板的背面。 第四焊盘电连接到第三焊盘。

公开(公告)号：US07778010B2

公开(公告)日：2010-08-17

申请号：US12497198

申请日：2009-07-02

Applicant: Motohiko Sato ,  Kazuhiro Hayashi ,  Akifumi Tosa ,  Kenji Murakami ,  Tomohide Yamada ,  Motonobu Kurahashi

Inventor： Motohiko Sato ,  Kazuhiro Hayashi ,  Akifumi Tosa ,  Kenji Murakami ,  Tomohide Yamada ,  Motonobu Kurahashi

IPC: H01G4/228

CPC classification number: H01G4/232 ,  H01G4/012 ,  H01G4/30 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10674 ,  H05K2201/10712 ,  Y10T29/435

Abstract: A capacitor comprising: a plurality of laminated dielectric layers; a plurality of inner electrode layers each disposed between mutually adjacent ones of the dielectric layers; and dummy electrode layers respectively disposed between the dielectric layers, disposed on sides closer to outer peripheral sides of the dielectric layers than to the inner electrode layers and disposed apart from the inner electrode layers.

Abstract translation: 一种电容器，包括：多个叠层电介质层; 多个内部电极层，各自设置在相互相邻的电介质层之间; 以及分别设置在电介质层之间的虚设电极层，其设置在比内部电极层更靠近电介质层的外周侧的一侧并且与内部电极层分离。

公开(公告)号：US07742314B2

公开(公告)日：2010-06-22

申请号：US11513034

申请日：2006-08-31

Applicant: Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Kohki Ogawa

Inventor： Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Kohki Ogawa

IPC: H05K1/11

CPC classification number: H05K1/185 ,  H01G2/06 ,  H01G4/40 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H05K1/0233 ,  H05K1/0234 ,  H05K3/4602 ,  H05K2201/10045 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A wiring board comprising: a board core (11) having a core main surface (12) and a core reverse surface (13); a capacitor (101, 101A, 101B, 101C, 101D, 101E, 101F, 101G, 101H, 101J, 1101, 1101′, 1101″, 1101′″, 1101″″, 1101′″″) having a capacitor main surface (102) and a capacitor reverse surface (103) and having a structure in which first inner electrode layers (141) and second inner electrode layers (142) are alternately laminated and arranged via a dielectric layer (105), the capacitor (101, 101A, 101B, 101C, 101D, 101E, 101F, 101G, 101H, 101J, 1101, 1101′, 1101″, 1101′″, 1101″″, 1101′″″) being accommodated in the board core (11) in a state in which the core main surface (12) and the capacitor main surface (102) are oriented on a same side; and a wiring laminated portion (31) having a structure in which interlayer insulating layers (33, 35) and conductor layers (42) are alternately laminated on the core main surface (12) and the capacitor main surface (102), wherein an inductor (251, 252, 253) or a resistor (301, 302, 311, 312, 321, 322) is formed on or in the capacitor (101, 101A, 101B, 101C, 101D, 101E, 101F, 101G, 101H, 101J, 1101, 1101′, 1101″, 1101′″, 1101″″, 1101′″″).

Abstract translation: 一种布线板，包括：具有芯主表面（12）和芯反向表面（13）的板芯（11）; 具有电容器主表面的电容器（101,101A，101B，101C，101D，101E，101F，101G，101H，101J，1101,1101,1101,1101“，1101”，1101“”，1101“ 102）和电容器反面（103），并且具有通过电介质层（105）交替层叠配置第一内电极层（141）和第二内电极层（142）的结构，电容器（101,101A ，101B，101C，101D，101E，101F，101G，101H，101J，1101,1101'，1101“，1101”“，1101”“，1101”“）被容纳在板芯（11） 其中所述芯主表面（12）和所述电容器主表面（102）位于同一侧; 以及具有层间绝缘层（33,35）和导体层（42）交替层叠在芯主表面（12）和电容器主表面（102）上的结构的布线层叠部分（31），其中电感器 （101,101A，101B，101C，101D，101E，101F，101G，101H，101J）中的电容器（251,102,253）或电阻器（301,302,311,312,321,322） ，1101,1101'，1101“，1101”“，1101”“，1101”“）。

公开(公告)号：US20100084175A1

公开(公告)日：2010-04-08

申请号：US12575504

申请日：2009-10-08

Applicant: Shinya SUZUKI ,  Kenichi SAITA ,  Shinya MIYAMOTO ,  Shinji YURI

Inventor： Shinya SUZUKI ,  Kenichi SAITA ,  Shinya MIYAMOTO ,  Shinji YURI

IPC: H05K1/16

CPC classification number: H05K1/185 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15312 ,  H05K1/0231 ,  H05K1/113 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/068 ,  H05K2201/096 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A component built-in wiring substrate (10) which includes: a core substrate (11); a plate-shaped component (101); a resin filling portion (92); and a wiring stacking portion (31), wherein, when viewed from the core principal surface (12) side, the projected area of the mounting area (32) is larger than the projected area of the plate-shaped component (101) and the resin filling portion, and the plate-shaped component and the resin filling portion are positioned directly below the mounting area (23), and wherein a value of the coefficient of thermal expansion (CTE α2) for a temperature range that is equal to or higher than the glass transition temperature of the resin filling portion is set to be larger than a value of the coefficient of thermal expansion of the plate-shaped component and smaller than a value of the coefficient of thermal expansion of the core substrate for the subject temperature range.

Abstract translation: 一种组件内置布线基板（10），包括：芯基板（11）; 板状部件（101）; 树脂填充部分（92）; 以及布线堆叠部（31），其中，当从所述芯主表面（12）侧观察时，所述安装区域（32）的所述投影面积大于所述板状部件（101）的投影面积，并且 树脂填充部分，并且板状部件和树脂填充部分位于安装区域（23）的正下方，并且其中等于或等于更高的温度范围的热膨胀系数（CTEα2）的值 将树脂填充部的玻璃化转变温度设定为大于板状部件的热膨胀系数的值，并且小于本体温度范围内的芯基板的热膨胀系数的值 。

公开(公告)号：US07675160B2

公开(公告)日：2010-03-09

申请号：US11648301

申请日：2006-12-29

Applicant: Sriram Dattaguru ,  Larry Binder ,  Cengiz A. Palanduz ,  Chris Jones ,  Dave Bach ,  Kaladhar Radhakrishnan ,  Timothe Litt

Inventor： Sriram Dattaguru ,  Larry Binder ,  Cengiz A. Palanduz ,  Chris Jones ,  Dave Bach ,  Kaladhar Radhakrishnan ,  Timothe Litt

IPC: H01L23/48

CPC classification number: H01L23/49827 ,  H01L23/13 ,  H01L23/50 ,  H01L23/642 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15159 ,  H01L2924/15787 ,  H05K1/0231 ,  H05K1/0262 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10545 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2924/00 ,  H01L2224/0401

Abstract: In some embodiments, an individual sub-assembly containing a ceramic interposer, silicon voltage regulator, and array capacitor is presented. In this regard, an apparatus is introduced having a table-shaped ceramic interposer containing conductive traces, a silicon voltage regulator coupled with contacts on a first surface of the ceramic interposer, and an array capacitor coupled with contacts on a second surface of the ceramic interposer. Other embodiments are also disclosed and claimed.

Abstract translation: 在一些实施例中，呈现包含陶瓷插入件，硅电压调节器和阵列电容器的单独子组件。 在这方面，引入了具有包含导电迹线的台式陶瓷插入器的装置，与陶瓷插入器的第一表面上的触点耦合的硅电压调节器，以及与陶瓷插入器的第二表面上的触点耦合的阵列电容器 。 还公开并要求保护其他实施例。

公开(公告)号：US07573697B2

公开(公告)日：2009-08-11

申请号：US11512247

申请日：2006-08-30

Applicant: Motohiko Sato ,  Kazuhiro Hayashi ,  Akifumi Tosa ,  Kenji Murakami ,  Tomohide Yamada ,  Motonobu Kurahashi

Inventor： Motohiko Sato ,  Kazuhiro Hayashi ,  Akifumi Tosa ,  Kenji Murakami ,  Tomohide Yamada ,  Motonobu Kurahashi

IPC: H01G4/228

CPC classification number: H01G4/232 ,  H01G4/012 ,  H01G4/30 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10674 ,  H05K2201/10712 ,  Y10T29/435

Abstract: A capacitor comprising: a plurality of laminated dielectric layers; a plurality of inner electrode layers each disposed between mutually adjacent ones of the dielectric layers; and dummy electrode layers respectively disposed between the dielectric layers, disposed on sides closer to outer peripheral sides of the dielectric layers than to the inner electrode layers and disposed apart from the inner electrode layers.

Abstract translation: 一种电容器，包括：多个叠层电介质层; 多个内部电极层，各自设置在相互相邻的电介质层之间; 以及分别设置在电介质层之间的虚设电极层，其设置在比内部电极层更靠近电介质层的外周侧的一侧并且与内部电极层分离。

公开(公告)号：US07473988B2

公开(公告)日：2009-01-06

申请号：US11513249

申请日：2006-08-31

Applicant: Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Jun Otsuka

Inventor： Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Jun Otsuka

IPC: H01L23/495

CPC classification number: H05K1/185 ,  H01G2/06 ,  H01G4/38 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/642 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/0231 ,  H05K3/4602 ,  H05K2201/10522 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A wiring board includes a substrate core, ceramic capacitors and a built-up layer. The substrate core has a housing opening portion therein which opens at a core main surface. The ceramic capacitors are accommodated in the housing opening portion and oriented such that the core main surface and a capacitor main surface of each capacitor face the same way. The built-up layer includes semiconductor integrated circuit element mounting areas at various locations on a surface thereof. In the substrate core, each ceramic capacitor is respectively disposed in an area corresponding to each semiconductor integrated circuit element mounting area.

Abstract translation: 布线板包括基板芯，陶瓷电容器和积层。 基板芯具有在芯主表面上开口的壳体开口部分。 陶瓷电容器容纳在壳体开口部分中并且取向为使得每个电容器的芯主表面和电容器主表面相同。 积层在其表面上的各个位置包括半导体集成电路元件安装区域。 在基板芯中，每个陶瓷电容器分别设置在对应于每个半导体集成电路元件安装区域的区域中。