公开(公告)号：US08465589B1

公开(公告)日：2013-06-18

申请号：US12701449

申请日：2010-02-05

Applicant: Prem Nath ,  Venugopala R. Basava ,  Ajay Kumar Kalla ,  Peter Alex Shevchuk ,  Mohan S. Misra

Inventor： Prem Nath ,  Venugopala R. Basava ,  Ajay Kumar Kalla ,  Peter Alex Shevchuk ,  Mohan S. Misra

IPC: C23C16/00

CPC classification number: H01L21/67173 ,  C23C14/0623 ,  C23C14/562 ,  C23C14/568 ,  H01L21/67236 ,  H01L21/6776

Abstract: A method of manufacture of CIGS photovoltaic cells and modules involves sequential deposition of copper indium gallium diselenide compounds in multiple thin sublayers to form a composite CIGS absorber layer of a desirable thickness greater than the thickness of each sublayer. In an embodiment, the method is adapted to roll-to-roll processing of CIGS PV cells. In an embodiment, the method is adapted to preparation of a CIGS absorber layer having graded composition through the layer. In a particular embodiment, the graded composition is enriched in copper at a base of the layer. In an embodiment, each CIGS sublayer is deposited by co-evaporation of copper, indium, gallium, and selenium which react in-situ to form CIGS.

Abstract translation: CIGS光伏电池和模块的制造方法包括将铜铟镓硒化合物顺序沉积在多个薄的子层中以形成具有比每个子层的厚度大的期望厚度的复合CIGS吸收层。 在一个实施例中，该方法适用于CIGS PV电池的卷对卷处理。 在一个实施方案中，该方法适于制备具有通过该层具有分级组成的CIGS吸收层。 在一个具体实施方案中，分级组合物在该层的底部富含铜。 在一个实施方案中，通过共同蒸发铜，铟，镓和硒沉积每个CIGS子层，其原位反应以形成CIGS。

公开(公告)号：US20130082833A1

公开(公告)日：2013-04-04

申请号：US13250027

申请日：2011-09-30

Applicant: Aninda Bhattacharya ,  Vivek Venugopal Badami ,  Rahul Srinivas Prabhu ,  Ajay Kumar Behera ,  Venkatesh Rajagopalan

Inventor： Aninda Bhattacharya ,  Vivek Venugopal Badami ,  Rahul Srinivas Prabhu ,  Ajay Kumar Behera ,  Venkatesh Rajagopalan

IPC: G06N5/04 ,  G08B23/00

CPC classification number: G01H1/003 ,  F01D21/003 ,  F05D2260/80 ,  F05D2270/707

Abstract: A method for monitoring health of airfoils is disclosed. The method comprises generating at least one feature alarm for a blade by fusing a plurality of features corresponding to the blade utilizing a fuzzy inference method. The fuzzy inference method comprises generating a plurality of intermediate values by fusing one or more combinations of the plurality of features utilizing a fuzzy logic method, and fusing the plurality of intermediate values utilizing a second level fuzzy logic method, wherein the at least one feature alarm is representative of the health of the blade.

Abstract translation: 公开了一种用于监测翼型的健康的方法。 该方法包括通过使用模糊推理方法融合与叶片对应的多个特征来为叶片产生至少一个特征报警。 所述模糊推理方法包括利用模糊逻辑方法融合所述多个特征的一个或多个组合来产生多个中间值，并且利用第二级模糊逻辑方法来融合所述多个中间值，其中所述至少一个特征报警 是刀片健康的代表。

公开(公告)号：US08407509B2

公开(公告)日：2013-03-26

申请号：US12901579

申请日：2010-10-11

Applicant: Rajeev Sharma ,  Ajay Kumar ,  Naresh Dhamija ,  Atul Gupta ,  Ajay K. Gaite ,  Llamparidhi l

Inventor： Rajeev Sharma ,  Ajay Kumar ,  Naresh Dhamija ,  Atul Gupta ,  Ajay K. Gaite ,  Llamparidhi l

IPC: G06F1/04 ,  G06F13/00 ,  G06F13/42

CPC classification number: G06F13/1689 ,  G06F13/4243

Abstract: A method for compensating for variations in timing of data sent to a processor on data bit lines relative to a strobe clock sent to the processor on a strobe clock line that can be used in a dual data rate (DDR) memory identifies discrete minimum and maximum time offset values for test data in selected data bit patterns for the data bit lines. The discrete minimum time offset value is the minimum timing adjustment required to allow the processor to receive the data in a steady-state condition during a data valid window of the strobe clock and the discrete maximum time offset value is a maximum timing adjustment required to allow the processor to receive the data in a steady-state condition during a data valid window of the strobe clock. The discrete minimum and maximum time offset values identify a valid range when the data bit lines supply data in a steady-state condition for latching into the processor by the strobe clock.

Abstract translation: 用于补偿在数据位线上相对于在双数据速率（DDR）存储器中使用的选通时钟线上发送到处理器的选通时钟的数据位线发送的数据的时序变化的方法，该方法能够识别离散的最小和最大值 用于数据位线的选定数据位模式中的测试数据的时间偏移值。 离散的最小时间偏移值是在选通时钟的数据有效窗口期间允许处理器在稳态条件下接收数据所需的最小定时调整，并且离散最大时间偏移值是允许允许的最大定时调整 所述处理器在所述选通时钟的数据有效窗口期间以稳态条件接收所述数据。 当数据位线在稳态条件下提供数据以通过选通时钟锁存到处理器中时，离散的最小和最大时间偏移值标识有效范围。

公开(公告)号：US20130001790A1

公开(公告)日：2013-01-03

申请号：US13170210

申请日：2011-06-28

Applicant: Ajay Kumar ,  Sahil S. Dabare ,  Ajay K. Gaite ,  Shyam S. Gupta

Inventor： Ajay Kumar ,  Sahil S. Dabare ,  Ajay K. Gaite ,  Shyam S. Gupta

IPC: H01L23/52 ,  H01L21/4763

CPC classification number: H01L23/50 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0612 ,  H01L2224/06515 ,  H01L2224/16225 ,  H01L2224/1712 ,  H01L2224/48 ,  H01L2224/4912 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/3862 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A system on a chip (SOC) includes a physical interface having first and second sets of interface pads. Interface pads from the first set are interleaved with interface pads from the second set. Additionally, the SOC is arranged for operation with a superset die having first and second personalities and has a physical interface with interface pads. The SOC uses a first number of interface pads in the first personality and a second number of interface pads in the second personality, where the first number is greater than the second number. A switch switches signals between the superset die and the physical interface and, in the second personality, switches signals to the physical interface so that interface pads in the second number of interface pads are interleaved with interface pads not in use in the second personality.

Abstract translation: 芯片上的系统（SOC）包括具有第一和第二组接口焊盘的物理接口。 来自第一组的接口焊盘与来自第二组的接口焊盘交错。 另外，SOC被配置为具有具有第一和第二个性的超级管芯的操作，并且具有与接口焊盘的物理接口。 SOC使用第一个人中的第一数量的接口焊盘和第二个人中的第二数量的接口焊盘，其中第一个数量大于第二个数量。 A开关在超级管芯和物理接口之间切换信号，并且在第二个性中将信号切换到物理接口，使得第二数量的接口焊盘中的接口焊盘与不在第二个性中使用的接口焊盘交错。

公开(公告)号：US20120322234A1

公开(公告)日：2012-12-20

申请号：US13160973

申请日：2011-06-15

Applicant: Madhava Rao YALAMANCHILI ,  Wei-Sheng LEI ,  Brad EATON ,  Saravjeet SINGH ,  Ajay KUMAR ,  Banqiu WU

Inventor： Madhava Rao YALAMANCHILI ,  Wei-Sheng LEI ,  Brad EATON ,  Saravjeet SINGH ,  Ajay KUMAR ,  Banqiu WU

IPC: H01L21/82 ,  C23F1/08

CPC classification number: H01L21/78 ,  B23K26/0624 ,  B23K26/364 ,  B23K26/40 ,  B23K2101/40 ,  B23K2103/172 ,  B23K2103/50 ,  H01L21/30655 ,  H01L21/3086 ,  H01L21/67207

Abstract: Methods of dicing substrates by both laser scribing and plasma etching. A method includes forming an in-situ mask with a plasma etch chamber by accumulating a thickness of plasma deposited polymer to protect IC bump surfaces from a subsequent plasma etch. Second mask materials, such as a water soluble mask material may be utilized along with the plasma deposited polymer. At least some portion of the mask is patterned with a femtosecond laser scribing process to provide a patterned mask with trenches. The patterning exposing regions of the substrate between the ICs in which the substrate is plasma etched to singulate the IC and the water soluble material layer washed off.

Abstract translation: 通过激光划线和等离子体蚀刻来切割基板的方法。 一种方法包括通过累积等离子体沉积聚合物的厚度来形成具有等离子体蚀刻室的原位掩模，以保护IC凸起表面免于随后的等离子体蚀刻。 可以与等离子体沉积的聚合物一起使用第二掩模材料，例如水溶性掩模材料。 用飞秒激光划线工艺对掩模的至少一部分进行图案化以提供具有沟槽的图案化掩模。 在IC之间的衬底的图案化曝光区域中，其中衬底被等离子体蚀刻以分离IC和水溶性材料层被洗掉。

公开(公告)号：US20120322233A1

公开(公告)日：2012-12-20

申请号：US13160891

申请日：2011-06-15

Applicant: Wei-Sheng LEI ,  Saravjeet SINGH ,  Madhava Rao Yalamanchili ,  Brad EATON ,  Ajay KUMAR

Inventor： Wei-Sheng LEI ,  Saravjeet SINGH ,  Madhava Rao Yalamanchili ,  Brad EATON ,  Ajay KUMAR

IPC: H01L21/82 ,  H01L21/3065

CPC classification number: H01L21/67207 ,  B23K26/0624 ,  B23K26/064 ,  B23K26/364 ,  B23K26/40 ,  B23K2101/40 ,  B23K2103/172 ,  B23K2103/50 ,  H01L21/30655 ,  H01L21/3081 ,  H01L21/67069 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327

Abstract: Methods of dicing substrates having a plurality of ICs. A method includes forming a mask comprising a water soluble material layer over the semiconductor substrate. The mask is patterned with a femtosecond laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the substrate between the ICs. The substrate is then etched through the gaps in the patterned mask to singulate the IC and the water soluble material layer washed off.

Abstract translation: 公开了具有多个IC的切割衬底的方法。 一种方法包括在半导体衬底上形成包含水溶性材料层的掩模。 用飞秒激光划线工艺对掩模进行图案化以提供具有间隙的图案化掩模。 图案化使IC之间的衬底的区域暴露。 然后将衬底通过图案化掩模中的间隙进行蚀刻，以对IC进行分离，并将水溶性材料层冲洗掉。

公开(公告)号：US20120305185A1

公开(公告)日：2012-12-06

申请号：US13455347

申请日：2012-04-25

Applicant: Saravjeet Singh ,  Graeme Jamieson Scott ,  Amitabh Sabharwal ,  Ajay Kumar

Inventor： Saravjeet Singh ,  Graeme Jamieson Scott ,  Amitabh Sabharwal ,  Ajay Kumar

IPC: B05C9/00 ,  B05C11/02

CPC classification number: H01J37/32082 ,  H01J37/321 ,  H01J37/32477 ,  H01J37/32623 ,  H01J37/32642 ,  H01J37/32651

Abstract: Embodiments of the present invention generally relate to a method and apparatus for plasma etching substrates and, more specifically, to a method and apparatus with protection for edges, sides and backs of the substrates being processed. Embodiments of the present invention provide an edge protection plate with an aperture smaller in size than a substrate being processed, wherein the edge protection plate may be positioned in close proximity to the substrate in a plasma chamber. The edge protection plate overlaps edges and/or sides on the substrate to provide protection to reflective coatings on the edge, sides, and back of the substrate.

Abstract translation: 本发明的实施例一般涉及用于等离子体蚀刻基板的方法和装置，更具体地说，涉及一种对被处理的基板的边缘，侧面和背面进行保护的方法和装置。 本发明的实施例提供了一种边缘保护板，该边缘保护板的尺寸小于被加工的基板，其中边缘保护板可以位于等离子体室中靠近基板的位置。 边缘保护板与基板上的边缘和/或侧面重叠以对基板的边缘，侧面和背面上的反射涂层提供保护。

公开(公告)号：US20120283342A1

公开(公告)日：2012-11-08

申请号：US13457893

申请日：2012-04-27

Applicant: Ajay Kumar Dalai ,  Venkateswara Rao Surisetty

Inventor： Ajay Kumar Dalai ,  Venkateswara Rao Surisetty

IPC: B01J21/18 ,  C07C29/158 ,  B01J27/051 ,  C07C29/157 ,  B82Y30/00

CPC classification number: B01J21/185 ,  B01J23/8993 ,  B01J35/002 ,  B01J35/0066 ,  B01J35/023 ,  B01J35/1014 ,  B01J35/1038 ,  B01J35/1061 ,  B01J37/0205 ,  B01J37/0207 ,  B01J37/20 ,  B82Y30/00 ,  C07C29/157 ,  C07C29/158 ,  C07C31/08

Abstract: The present application includes alkali metal-promoted trimetallic catalysts for higher alcohol synthesis from synthesis gas, the catalyst comprising a catalyst of Formula (1): A-M1-M2-M3.

Abstract translation: 本申请包括用于由合成气合成高级醇的碱金属促进的金属催化剂，所述催化剂包含式（1）的催化剂：A-M1-M2-M3。

公开(公告)号：US08277931B1

公开(公告)日：2012-10-02

申请号：US12815483

申请日：2010-06-15

Applicant: Ajay Kumar

Inventor： Ajay Kumar

IPC: B32B27/32 ,  B32B9/04 ,  B32B27/40 ,  B32B17/06 ,  B32B9/00 ,  B32B27/34

CPC classification number: B32B27/12 ,  B32B13/12 ,  B32B37/12 ,  B32B38/0032 ,  B32B2038/0028 ,  B32B2038/166 ,  B32B2307/5825 ,  B32B2307/724 ,  B32B2307/7265 ,  B32B2309/105 ,  B32B2315/085 ,  B32B2315/18 ,  B32B2607/00 ,  Y10T428/249982 ,  Y10T428/249991 ,  Y10T428/26 ,  Y10T428/31504 ,  Y10T428/31551 ,  Y10T428/31616 ,  Y10T428/31623 ,  Y10T428/31645 ,  Y10T428/31739 ,  Y10T428/31743 ,  Y10T428/31855

Abstract: The subject invention relates to a facer which is comprised of a breathable film and a glass mat, wherein the breathable film and the glass mat are bonded together with an adhesive, wherein the breathable film is comprised of a breathable polymeric material selected from the group consisting of polyolefins, nylons, polyesters, and thermoplastic elastomers, and wherein the facer is water resistant. The facers of this invention can be employed in manufacturing construction board, such as polyisocyanurate boards, polystyrene boards, or gypsum boards. The present invention accordingly more specifically discloses a construction board which is comprised of a rigid sheet and a facer, wherein the facer is bonded to at least one side of said rigid sheet, wherein the rigid sheet is comprised of a member selected from the group consisting of gypsum, blown polystyrene, and polyisocyanurate, wherein the facer is comprised of a breathable polymeric material selected from the group consisting of polyolefins, nylons, polyesters, and thermoplastic elastomers, wherein the breathable polymeric material is bonded to another substrate, such as a glass mat with an adhesive, and wherein the facer is water resistant.

Abstract translation: 本发明涉及一种由透气膜和玻璃垫构成的面，其中透气膜和玻璃垫用粘合剂粘合在一起，其中透气膜由透气聚合物材料组成，该材料选自 的聚烯烃，尼龙，聚酯和热塑性弹性体，并且其中该面是防水的。 本发明的面具可用于制造施工板，如聚异氰脲酸酯板，聚苯乙烯板或石膏板。 因此，本发明更具体地公开了一种由刚性片和面构成的构造板，其中所述平面结合到所述刚性片的至少一侧，其中所述刚性片由选自以下的构件组成： 石膏，吹塑聚苯乙烯和聚异氰脲酸酯，其中该面由选自聚烯烃，尼龙，聚酯和热塑性弹性体的透气聚合材料组成，其中透气聚合物材料结合到另一基底如玻璃 具有粘合剂的垫，并且其中所述面是防水的。

公开(公告)号：US08245233B2

公开(公告)日：2012-08-14

申请号：US12335690

申请日：2008-12-16

Applicant: Anis M. Abdul ,  Brent William Jacobs ,  Ajay Kumar Mahajan ,  Atit D. Patel

Inventor： Anis M. Abdul ,  Brent William Jacobs ,  Ajay Kumar Mahajan ,  Atit D. Patel

IPC: G06F9/46

CPC classification number: G06F9/5011

Abstract: A method, a system and a computer program product for selecting a primary controller for a server system based on the services offered by each controller. A primary controller designator (PCD) utility determines the relative importance of a controller based upon the services provided by the controller and the weighted importance assigned to these services. The PCD utility classifies the services provided by a system-controller according to the following: (1) the number of OS partitions a system-controller is able to communicate with; and (2) the number of hardware devices that a controller has access to. The importance of the services is determined by the host OS partition information and the degree of importance of a partition that utilizes/requires the particular service(s). The PCD utility designates a controller as a “Primary” if the designated “Primary” is capable of providing services that are required for the most important OS partitions, according to the classification of controller services.

Abstract translation: 一种用于基于由每个控制器提供的服务来选择用于服务器系统的主控制器的方法，系统和计算机程序产品。 主控制器指示符（PCD）实用程序根据控制器提供的服务和分配给这些服务的加权重要性来确定控制器的相对重要性。 PCD实用程序根据以下内容对系统控制器提供的服务进行分类：（1）系统控制器能够通信的OS分区数; 和（2）控制器访问的硬件设备的数量。 服务的重要性由主机OS分区信息和利用/要求特定服务的分区的重要程度决定。 如果指定的“主”能够提供最重要的OS分区所需的服务，则根据控制器服务的分类，PCD实用程序将控制器指定为“主”。