公开(公告)号：US20190123410A1

公开(公告)日：2019-04-25

申请号：US15880957

申请日：2018-01-26

Applicant: Integrated Device Technology, Inc.

Inventor： Samet Zihir ,  Tumay Kanar ,  Naveen Krishna Yanduru

IPC: H01P1/02 ,  H05K1/02 ,  H01P3/08 ,  H03H7/38

Abstract: An apparatus includes a plurality of conductive layers and a plurality of traces configured to carry a plurality of signals through a change of direction. The traces may be routed parallel to each other in a first trace segment in a first of the conductive layers toward the change of direction. The traces may be routed parallel to each other in a second trace segment in a second of the conductive layers in the change of direction. One of the traces in a third trace segment in the first conductive layer may cross over another of the traces in the second trace segment in the second conductive layer in the change of direction. The traces may be routed parallel to each other in the third trace segment in the first conductive layer away from the change of direction.

公开(公告)号：US10236870B2

公开(公告)日：2019-03-19

申请号：US15834547

申请日：2017-12-07

Applicant: Integrated Device Technology, Inc.

Inventor： Zhigang Hu ,  Hui Yu ,  Shaokang Wang ,  Yuan Zhang ,  Yue Yu

IPC: G11C5/04 ,  G11C7/10 ,  H03K5/15

Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate a plurality of delayed signals each as a copy of an input signal shifted in time by a sequence of respective delays based on a control signal. At least two of the respective delays may have a different duration. The first circuit may also be configured to change a number of driver signals that are active during each delay in the sequence of respective delays based on the input signal and the plurality of delayed signals to control a slew rate of an output signal. The second circuit may be configured to drive the output signal in response to the driver signals.

公开(公告)号：US10235295B1

公开(公告)日：2019-03-19

申请号：US15247854

申请日：2016-08-25

Applicant: Integrated Device Technology, Inc.

Inventor： Mohammad Shahanshah Akhter

IPC: G06F12/08 ,  G06F12/0873 ,  G06F13/16 ,  G06F9/46

Abstract: Scalable Coherent Apparatus and Method have been disclosed. In one implementation a dual directory approach is used to implement scalable coherent accesses in a heterogeneous system. A transaction identification mapping for coherent RapidIO memory transactions between a plurality of external hardware processing elements is used. Source transaction identification encoding is a combination of bits from two advanced extensible interface identifications. Target transaction identification is decoded into a combination of bits for two advanced extensible interface identifications.

公开(公告)号：US20190058392A1

公开(公告)日：2019-02-21

申请号：US15897448

申请日：2018-02-15

Applicant: INTEGRATED DEVICE TECHNOLOGY, INC.

Inventor： Lijie ZHAO ,  Yue WANG ,  Stephen ULBRICH

IPC: H02M1/36 ,  H02M7/217 ,  H02J50/12 ,  H02J7/02 ,  H02M1/00

CPC classification number: H02M1/36 ,  H02J7/025 ,  H02J50/12 ,  H02M7/217 ,  H02M2001/0006

Abstract: A rectifier circuit can include a plurality of FETs arranged as a rectifier; and a start-up circuit applied to each of the plurality of FETs that turn each of the FETs off during a circuit startup period, wherein the start-up circuit provides a large impedance for low power dissipation during normal operation of the rectifier.

公开(公告)号：US20190028105A1

公开(公告)日：2019-01-24

申请号：US16139340

申请日：2018-09-24

Applicant: Integrated Device Technology, Inc.

Inventor： Hui Li ,  Teck-Chuan Ng ,  Stephen E. Aycock

IPC: H03K21/02 ,  H03M3/00

Abstract: An apparatus includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first code by counting a number of cycles of an input clock signal during a period. The period may be determined by an output clock signal and a second code. The second circuit may be configured to generate a third code by a delta-sigma modulation of the first code. The third circuit may be configured to generate the output clock signal in response to the third code. An accuracy of a frequency of the output clock signal may be determined by a current value of the second code.

公开(公告)号：US20190013054A1

公开(公告)日：2019-01-10

申请号：US16043694

申请日：2018-07-24

Applicant: Integrated Device Technology, Inc.

Inventor： Alejandro F. Gonzalez

IPC: G11C7/22 ,  G11C5/04 ,  G11C7/12 ,  G06F13/40 ,  G11C7/10

Abstract: An apparatus includes a plurality of memory devices and a control circuit. The control circuit may be configured to enable a plurality of access modes for the plurality of memory devices. In a one-channel mode, all of the memory devices are accessed using a single selectable channel. In a two-channel mode, a first portion of the plurality of memory devices is accessed using a first channel and a second portion of the plurality of memory devices is accessed using a second channel.

公开(公告)号：US10132650B2

公开(公告)日：2018-11-20

申请号：US14603296

申请日：2015-01-22

Applicant: Integrated Device Technology, Inc.

Inventor： Gustavo J. Mehas ,  David F. Wilson ,  Nicholaus W. Smith

IPC: H02J5/00 ,  G01D5/20 ,  H02J50/60 ,  H04B5/00 ,  H02J50/12 ,  H02J50/70 ,  H02J50/90

Abstract: A wireless power transmitter may include a transmit coil configured to generate a wireless power signal for wireless power transfer, at least one secondary sensing coil configured to generate a signal responsive to a magnetic flux field generated during the wireless power transfer, and control logic configured to detect at least one condition of a wireless power transfer system responsive to detecting distortion in the magnetic flux field from the at least one signal received from the secondary sensing coil. A related method may include generating with a wireless power transmitter a wireless power signal, generating with a plurality of secondary sensing coils one or more signals responsive to a magnetic flux field generated during the wireless power transfer, and detecting at least one condition of a wireless power transfer system responsive to the one or more signals generated by the plurality of secondary sensing coils.

公开(公告)号：US20180309324A1

公开(公告)日：2018-10-25

申请号：US16024487

申请日：2018-06-29

Applicant: Integrated Device Technology, Inc.

Inventor： Manjit SINGH ,  Siamak BASTAMI ,  David WILSON

IPC: H02J50/10 ,  H02J7/02 ,  H02J50/20 ,  H02J5/00 ,  H04B5/00 ,  H02J50/60

CPC classification number: H02J50/10 ,  H02J5/005 ,  H02J7/025 ,  H02J50/20 ,  H02J50/60 ,  H04B5/0037 ,  H04B5/0068 ,  H04B5/0081

Abstract: An inductive wireless power transfer device comprises a transmitter that comprises a transmit coil configured to generate a wireless power signal to a coupling region in response to an input voltage, and a modulator configured to modulate the wireless power signal and encode data with the wireless power signal to establish a back-channel communication link from the transmitter to a receiver. An inductive wireless power receiving device comprises a receiver that comprises a receive coil configured to generate a time varying signal in response to receiving a modulated wireless power signal from a transmitter in a coupling region, and a demodulator configured to demodulate the modulated wireless power signal from an established back-channel communication link from the transmitter to a receiver. Related inductive wireless power transfer systems and methods for back-channel communication from the transmitter to the receiver of an inductive wireless power transfer system are disclosed.

公开(公告)号：US20180288718A1

公开(公告)日：2018-10-04

申请号：US15475648

申请日：2017-03-31

Applicant: Integrated Device Technology, Inc.

Inventor： Jagdeep Bal ,  Elie Ayache ,  Eduard Van Keulen

IPC: H04W56/00 ,  H04L7/04

CPC classification number: H04W56/0015 ,  H04L7/04

Abstract: An apparatus includes a first independently clocked device and one or more second independently clocked devices. The first independently clocked device may comprise a clock generator. The clock generator may be configured to generate a clock signal. The first independently clocked device may be configured to wirelessly broadcast a synchronization signal based on the clock signal. The one or more second independently clocked devices may each comprise respective clock generators. The one or more second independently clocked devices may (a) be configured to receive the synchronization signal from the first independently clocked device and (b) synchronize the respective clock generators to the clock signal of the first independently clocked device in response to the synchronization signal.

公开(公告)号：US20180284835A1

公开(公告)日：2018-10-04

申请号：US15475328

申请日：2017-03-31

Applicant: Integrated Device Technology, Inc.

Inventor： Jagdeep Bal ,  Ron Wade

IPC: G06F1/12 ,  G06F1/08 ,  G06F13/42

CPC classification number: G06F1/12 ,  G06F1/08 ,  G06F13/4291

Abstract: An apparatus includes a plurality of independently clocked devices and a low frequency beacon. Each of the plurality of independently clocked devices has a respective local clock generator. The low frequency beacon communicates a low frequency synchronization signal to each of the independently clocked devices. The respective local clock generators of the plurality of independently clocked devices are generally synchronized using the low frequency synchronization signal.