公开(公告)号：US06802935B2

公开(公告)日：2004-10-12

申请号：US10103618

申请日：2002-03-21

Applicant: Yi-Lung Cheng ,  Hui-Chi Lin ,  Szu-An Wu ,  Ying-Lang Wang

Inventor： Yi-Lung Cheng ,  Hui-Chi Lin ,  Szu-An Wu ,  Ying-Lang Wang

IPC: B65G4907

CPC classification number: H01L21/67167 ,  C23C16/4405 ,  C23C16/54 ,  H01L21/67196 ,  Y10S414/135

Abstract: A semiconductor processing apparatus and method are disclosed herein, including a plurality of process chambers, wherein at least one semiconductor processing operation occurs within each process chamber among the plurality of process chambers. Additionally, the apparatus and method disclosed herein include a robot mechanism for rotating each process chamber among the plurality of process chambers upon completion of an associated semiconductor processing operation. Such a robot mechanism may comprise a plurality of robots. Specifically, such a plurality of robots may include six robots configured on an associated carousel.

Abstract translation: 本文公开了包括多个处理室的半导体处理装置和方法，其中在多个处理室中的每个处理室内发生至少一个半导体处理操作。 此外，本文公开的装置和方法包括机器人机构，用于在完成相关联的半导体处理操作时在多个处理室中旋转每个处理室。 这样的机器人机构可以包括多个机器人。 具体地说，这样的多个机器人可以包括配置在相关转盘上的六个机器人。

公开(公告)号：US06784077B1

公开(公告)日：2004-08-31

申请号：US10270973

申请日：2002-10-15

Applicant: Shih-Chi Lin ,  Chih Chung Lee ,  Guey Bao Huang ,  Szu-An Wu ,  Ying Lang Wang ,  Chun Chun Yeh

Inventor： Shih-Chi Lin ,  Chih Chung Lee ,  Guey Bao Huang ,  Szu-An Wu ,  Ying Lang Wang ,  Chun Chun Yeh

IPC: H01L2176

CPC classification number: H01L21/76224

Abstract: A method of forming a silicon oxide, shallow trench isolation (STI) region, featuring a silicon rich, silicon oxide layer used to protect the STI region from a subsequent wet etch procedure, has been developed. The method features depositing a silicon oxide layer via PECVD procedures, without RF bias, using a high silane to oxygen ratio, resulting in a silicon rich, silicon oxide layer, located surrounding the STI region. The low etch rate of the silicon rich, silicon oxide layer, protect the silicon oxide STI region from buffered hydrofluoric wet etch procedures, used for removal of a dioxide pad layer.

Abstract translation: 已经开发了一种形成氧化硅，浅沟槽隔离（STI）区域的方法，其特征在于用于保护STI区域免受后续湿蚀刻过程的富硅氧化硅层。 该方法的特征是通过PECVD方法沉积氧化硅层，无需RF偏压，使用高硅烷与氧气比，导致位于STI区周围的富含硅的氧化硅层。 富硅氧化硅层的低蚀刻速率保护硅氧化物STI区域免受用于去除二氧化物焊盘层的缓冲氢氟酸湿蚀刻工艺。

公开(公告)号：US06586347B1

公开(公告)日：2003-07-01

申请号：US09978229

申请日：2001-10-16

Applicant: Chung-Shi Liu ,  Hui-Ling Wang ,  Szu-An Wu ,  Chun-Ching Tsan ,  Ying Lang Wang ,  Tong Hua Kuan

Inventor： Chung-Shi Liu ,  Hui-Ling Wang ,  Szu-An Wu ,  Chun-Ching Tsan ,  Ying Lang Wang ,  Tong Hua Kuan

IPC: H01L2131

CPC classification number: H01L21/76801 ,  H01L21/76832

Abstract: An improved composite dielectric structure and method of forming thereof which prevents delamination of FSG (F-doped SiO2) and allows FSG to be used as the interlevel dielectric between successive conducting interconnection patterns in multilevel integrated circuit structures has been developed. The composite dielectric structure comprises FSG, undoped silicon oxide (optional), silicon-rich silicon oxide and silicon nitride. The silicon-rich silicon oxide layer having a thickness between about 1000 and 2000 Angstroms prevents reaction of F atoms from the FSG layer with the silicon nitride layer during subsequent manufacturing heat treatment cycles and prevents the deleterious formation of delamination bubbles which cause peeling of the FSG layer.

Abstract translation: 已经开发了一种改进的复合电介质结构及其形成方法，其防止FSG（F掺杂SiO 2）的分层并且允许FSG用作多电平集成电路结构中的连续导电互连图案之间的层间电介质。 复合电介质结构包括FSG，未掺杂的氧化硅（可选），富硅氧化硅和氮化硅。 厚度在约1000和2000埃之间的富含硅的氧化硅层防止了F原子与氮化硅层在随后的制造热处理循环中的反应，并且防止了导致FSG剥离的分层气泡的有害形成 层。

公开(公告)号：US06573189B1

公开(公告)日：2003-06-03

申请号：US10044859

申请日：2001-11-07

Applicant: Shih-Chi Lin ,  Ming-Hua Yu ,  Szu-An Wu

Inventor： Shih-Chi Lin ,  Ming-Hua Yu ,  Szu-An Wu

IPC: H01L21302

CPC classification number: H01L21/0276

Abstract: A new method of preventing photoresist footing by forming a silicon oxynitride ARC layer having an oxygen-rich surface is described. An insulating layer is provided on a substrate. A metal layer is deposited overlying the insulating layer. A silicon oxynitride antireflective coating layer having an oxygen-rich surface is deposited overlying the metal layer. A photoresist mask is formed overlying the antireflective coating layer wherein the antireflective coating layer prevents photoresist footing. The antireflective coating layer and the metal layer are etched away where they are not covered by the photoresist mask to complete formation of metal lines in the fabrication of an integrated circuit.

Abstract translation: 描述了通过形成具有富氧表面的氧氮化硅ARC层来防止光致抗蚀剂底脚的新方法。 绝缘层设置在基板上。 沉积在绝缘层上的金属层。 具有富氧表面的氧氮化硅抗反射涂层沉积在金属层上。 形成覆盖抗反射涂层的抗蚀剂掩模，其中抗反射涂层防止光致抗蚀剂底脚。 抗反射涂层和金属层被蚀刻掉，其中它们不被光致抗蚀剂掩模覆盖，以在集成电路的制造中完成金属线的形成。

公开(公告)号：US08470390B2

公开(公告)日：2013-06-25

申请号：US11972785

申请日：2008-01-11

Applicant: Yu-Sheng Wang ,  Shih-Ho Lin ,  Kei-Wei Chen ,  Szu-An Wu ,  Ying-Lang Wang

Inventor： Yu-Sheng Wang ,  Shih-Ho Lin ,  Kei-Wei Chen ,  Szu-An Wu ,  Ying-Lang Wang

IPC: B05D5/12 ,  C23C14/00

CPC classification number: H01L21/76814 ,  H01L21/02063 ,  H01L21/76828 ,  H01L21/76843

Abstract: A method of forming an integrated circuit structure includes providing a substrate; forming a metal feature over the substrate; forming a dielectric layer over the metal feature; and forming an opening in the dielectric layer. At least a portion of the metal feature is exposed through the opening. An oxide layer is accordingly formed on an exposed portion of the metal feature. The method further includes, in a production tool having a vacuum environment, performing an oxide-removal process to remove the oxide layer. Between the step of forming the opening and the oxide-removal process, no additional oxide-removal process is performed to the metal feature outside the production tool. The method further includes, in the production tool, forming a diffusion barrier layer in the opening, and forming a seed layer on the diffusion barrier layer.

Abstract translation: 形成集成电路结构的方法包括提供基板; 在衬底上形成金属特征; 在金属特征上形成介电层; 并在介电层中形成开口。 金属特征的至少一部分通过开口露出。 相应地，在金属特征的暴露部分上形成氧化物层。 该方法还包括在具有真空环境的生产工具中进行氧化物去除工艺以去除氧化物层。 在形成开口的步骤和氧化物去除工艺之间，对生产工具外部的金属特征没有进行额外的氧化物去除处理。 该方法还包括在生产工具中在开口中形成扩散阻挡层，并在扩散阻挡层上形成种子层。

公开(公告)号：US20110006354A1

公开(公告)日：2011-01-13

申请号：US12754761

申请日：2010-04-06

Applicant: Shiu-Ko JANGJIAN ,  Szu-An WU ,  Sheng-Wen CHEN

Inventor： Shiu-Ko JANGJIAN ,  Szu-An WU ,  Sheng-Wen CHEN

IPC: H01L29/78 ,  H01L29/49 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66583 ,  H01L29/7833

Abstract: A semiconductor device structure, for improving the metal gate leakage within the semiconductor device. A structure for a metal gate electrode for a n-type Field Effect Transistor includes a capping layer; a first metal layer comprising Ti and Al over the capping layer; a metal oxide layer over the first metal layer; a barrier layer over the metal oxide layer; and a second metal layer over the barrier layer.

Abstract translation: 一种用于改善半导体器件内的金属栅极泄漏的半导体器件结构。 用于n型场效应晶体管的金属栅电极的结构包括封盖层; 在覆盖层上包含Ti和Al的第一金属层; 第一金属层上的金属氧化物层; 金属氧化物层上的阻挡层; 和阻挡层上的第二金属层。

公开(公告)号：US20090181164A1

公开(公告)日：2009-07-16

申请号：US11972785

申请日：2008-01-11

Applicant: Yu-Sheng Wang ,  Shih-Ho Lin ,  Kei-Wei Chen ,  Szu-An Wu ,  Ying-Lang Wang

Inventor： Yu-Sheng Wang ,  Shih-Ho Lin ,  Kei-Wei Chen ,  Szu-An Wu ,  Ying-Lang Wang

IPC: H05K3/46

CPC classification number: H01L21/76814 ,  H01L21/02063 ,  H01L21/76828 ,  H01L21/76843

Abstract: A method of forming an integrated circuit structure includes providing a substrate; forming a metal feature over the substrate; forming a dielectric layer over the metal feature; and forming an opening in the dielectric layer. At least a portion of the metal feature is exposed through the opening. An oxide layer is accordingly formed on an exposed portion of the metal feature. The method further includes, in a production tool having a vacuum environment, performing an oxide-removal process to remove the oxide layer. Between the step of forming the opening and the oxide-removal process, no additional oxide-removal process is performed to the metal feature outside the production tool. The method further includes, in the production tool, forming a diffusion barrier layer in the opening, and forming a seed layer on the diffusion barrier layer

Abstract translation: 形成集成电路结构的方法包括提供基板; 在衬底上形成金属特征; 在金属特征上形成介电层; 并在介电层中形成开口。 金属特征的至少一部分通过开口露出。 相应地，在金属特征的暴露部分上形成氧化物层。 该方法还包括在具有真空环境的生产工具中进行氧化物去除工艺以去除氧化物层。 在形成开口的步骤和氧化物去除工艺之间，对生产工具外部的金属特征没有进行额外的氧化物去除处理。 该方法还包括在生产工具中在开口中形成扩散阻挡层，并在扩散阻挡层上形成种子层

公开(公告)号：US20060196417A1

公开(公告)日：2006-09-07

申请号：US11070149

申请日：2005-03-03

Applicant: Chia-Hui Lin ,  Shih-Hao Lo ,  Tsang-Yu Liu ,  Szu-An Wu ,  Cheng-Hui Yang ,  Yi-Fang Lai ,  Chien Lin

Inventor： Chia-Hui Lin ,  Shih-Hao Lo ,  Tsang-Yu Liu ,  Szu-An Wu ,  Cheng-Hui Yang ,  Yi-Fang Lai ,  Chien Lin

IPC: C23C16/00

CPC classification number: C23C16/45574 ,  C23C16/4558

Abstract: Gas distribution systems for deposition processes and methods of using the same. A substrate support member holding a substrate is disposed in a processing chamber. A plurality of first and second gas nozzles is connected to a gas distribution ring disposed in the processing chamber. The first gas nozzles provide a first reactant gas and include at least first and second outlet apertures. The second gas nozzles provide a second reactant gas and include third outlet apertures. The first outlet aperture is larger than the second outlet aperture, such that the first gas nozzle with the first outlet aperture creates an increased gas flow adjacent to a determined portion of the substrate to increase deposition from the first reactant gas on the determined portion of the substrate.

Abstract translation: 用于沉积工艺的气体分配系统及其使用方法。 保持基板的基板支撑构件设置在处理室中。 多个第一和第二气体喷嘴连接到设置在处理室中的气体分配环。 第一气体喷嘴提供第一反应气体并且包括至少第一和第二出口孔。 第二气体喷嘴提供第二反应气体并且包括第三出口孔。 第一出口孔大于第二出口孔，使得具有第一出口孔的第一气体喷嘴产生与衬底的确定部分相邻的增加的气流，以增加第一反应气体在所确定的部分上的沉积 基质。

公开(公告)号：US06985222B2

公开(公告)日：2006-01-10

申请号：US10423379

申请日：2003-04-25

Applicant: Hsi-Kuei Cheng ,  Chu-Chang Chen ,  Ting-Chun Wang ,  Szu-An Wu ,  Ying-Lang Wang ,  Hsien-Ping Feng

Inventor： Hsi-Kuei Cheng ,  Chu-Chang Chen ,  Ting-Chun Wang ,  Szu-An Wu ,  Ying-Lang Wang ,  Hsien-Ping Feng

IPC: G01N21/88

CPC classification number: G01N21/55 ,  G01N21/8422 ,  G01N2201/0227

Abstract: A system and method for detecting chamber leakage by measuring the reflectivity of an oxidized thin film. In a preferred embodiment, a method of detecting leaks in a chamber includes providing a first monitor workpiece, placing the first monitor workpiece in the chamber, and forming at least one film on the first monitor workpiece. The reflectivity of the least one film of the first monitor workpiece is measured, wherein the reflectivity indicates whether there are leaks in the at least one seal of the chamber. In another embodiment, the method includes providing a second monitor workpiece, placing the second monitor workpiece in the chamber, and forming at least one film on the second monitor workpiece. The reflectivity of the at least one film of the second monitor workpiece is measured, and the second monitor workpiece film reflectivity is compared to the first monitor workpiece film reflectivity.

Abstract translation: 通过测量氧化薄膜的反射率来检测室泄漏的系统和方法。 在优选实施例中，检测腔室泄漏的方法包括提供第一监测工件，将第一监测器工件放置在腔室中，以及在第一监测器工件上形成至少一个膜。 测量第一监视器工件的至少一个膜的反射率，其中反射率指示在室的至少一个密封件中是否有泄漏。 在另一个实施例中，该方法包括提供第二监视器工件，将第二监视器工件放置在腔室中，以及在第二监视器工件上形成至少一个膜。 测量第二监测工件的至少一个膜的反射率，并将第二监测工件膜反射率与第一监测工件膜反射率进行比较。

公开(公告)号：US06979656B2

公开(公告)日：2005-12-27

申请号：US10729217

申请日：2003-12-04

Applicant: Shiu-Ko Jangjian ,  Jun Wu ,  Chi-Wen Liu ,  Ying-Lung Wang ,  Yi-Lung Cheng ,  Michael Chang ,  Szu-An Wu

Inventor： Shiu-Ko Jangjian ,  Jun Wu ,  Chi-Wen Liu ,  Ying-Lung Wang ,  Yi-Lung Cheng ,  Michael Chang ,  Szu-An Wu

IPC: H01L21/31 ,  H01L21/316 ,  H01L21/76 ,  H01L23/532 ,  H01L23/58

CPC classification number: H01L23/5329 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02131 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76835 ,  H01L21/7684 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a dielectric layer provides for use of a carbon source material separate from a halogen source material when forming a carbon and halogen doped silicate glass dielectric layer. The use of separate carbon and halogen source materials provides enhanced process latitude when forming the carbon and halogen doped silicate glass dielectric layer. Such a carbon and halogen doped silicate glass dielectric layer having a dielectric constant greater than about 3.0 is particularly useful as an intrinsic planarizing stop layer within a damascene method. A bilayer dielectric layer construction comprising a carbon and halogen doped silicate glass and a carbon doped silicate glass dielectric layer absent halogen doping is useful within a dual damascene method.

Abstract translation: 制造电介质层的方法提供了当形成碳和卤素掺杂的硅酸盐玻璃介电层时与卤素源材料分开的碳源材料的使用。 当形成碳和卤素掺杂的硅酸盐玻璃介电层时，使用单独的碳和卤素源材料提供了增强的工艺自由度。 具有大于约3.0的介电常数的这种碳和卤素掺杂的硅酸盐玻璃介电层特别适用于镶嵌法中的本征平面化停止层。 包含碳和卤素掺杂的硅酸盐玻璃的双层电介质层结构和不含卤素掺杂的碳掺杂的硅酸盐玻璃介电层在双镶嵌方法中是有用的。