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41.发明申请公开(公告)号：US20250113591A1
公开(公告)日：2025-04-03
申请号：US18479005
申请日：2023-09-30
Applicant: Texas Instruments Incorporated
Inventor： Alexei Sadovnikov
IPC: H01L29/78 , H01L21/265 , H01L29/66
Abstract: A method forms an integrated circuit, by steps including, in a first implant, forming in a semiconductor substrate a first and second region of a first semiconductor type, each of the first and second region having a first dopant concentration; in a second implant, forming in the semiconductor substrate a third and fourth region of the first semiconductor type, the third region at least partially overlapping the first region and the fourth region at least partially overlapping the second region, each of the third and fourth region having a second dopant concentration different than the first dopant concentration; forming a transistor source within the first and third regions; and forming one of a diode anode or a diode cathode in the second and fourth regions.
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公开(公告)号：US20250113558A1
公开(公告)日：2025-04-03
申请号：US18374517
申请日：2023-09-28
Applicant: Texas Instruments Incorporated
Inventor： Gowrisankar Damarla , Robert Cassel , Zachary Katz , Ryan Rust
IPC: H01L29/06 , H01L29/40 , H01L29/423 , H01L29/66 , H01L29/78
Abstract: A method of forming an integrated circuit includes forming a first trench that extends into the semiconductor substrate. A silicon nitride layer is deposited over the semiconductor substrate. The silicon nitride layer extends into the first trench. A second trench is formed that extends through the silicon nitride layer into the semiconductor substrate. The second trench is spaced apart from the first trench. An oxide layer is formed that fills the second trench. The silicon nitride layer outside the first trench is removed.
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公开(公告)号：US20250112629A1
公开(公告)日：2025-04-03
申请号：US18374202
申请日：2023-09-28
Applicant: Texas Instruments Incorporated
Inventor： Eung Jung Kim , Xiaochun Zhao , Abidur Rahman , Sualp Aras
IPC: H03K17/0812
Abstract: An example apparatus includes: a first transistor having a first terminal, a second terminal, and a control terminal; a second transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor coupled to the first terminal of the first transistor, the second terminal of the second transistor coupled to the second terminal of the first transistor; first driver circuitry having a terminal coupled to the control terminal of the first transistor; second driver circuitry having a terminal coupled to the control terminal of the second transistor; and gate balancing circuitry having a first terminal and a second terminal, the first terminal of the gate balancing circuitry coupled to the control terminal of the first transistor and the terminal of the first driver circuitry, the second terminal of the gate balancing circuitry coupled to the control terminal of the second transistor.
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公开(公告)号：US20250112568A1
公开(公告)日：2025-04-03
申请号：US18477955
申请日：2023-09-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： RAJAN LAKSHMI NARASIMHA , DAVID P MAGEE
Abstract: A method includes receiving a first measurement signal representing a first time between transitions of a motor commutation state. The method further includes receiving a second measurement signal representing a second time between transitions of a motor floating terminal voltage. The method further includes determining a motor speed state based on a combination of the first and second measurement signals, determining a motor commutation state based on the motor speed state and the motor floating terminal voltage; and providing a control signal to a motor inverter based on the motor commutations state.
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公开(公告)号：US20250112552A1
公开(公告)日：2025-04-03
申请号：US18477721
申请日：2023-09-29
Applicant: Texas Instruments Incorporated
Inventor： Hongcheng Xu
Abstract: A voltage monitoring circuit is configured to monitor the input voltage in a power converter and to assert a reset signal to disable operation of the power converter in response to the input voltage falling below a threshold level. The voltage monitoring circuit may include a power-on-reset (POR) block that asserts the reset signal in response to the input voltage falling below a first threshold at a first rate, and a brown-out block that asserts the reset signal in response to the input voltage falling below a second threshold at a faster second rate (e.g., the input voltage falls quickly to zero or near zero such as during a brown-out event). The brown-out block includes a backup supply voltage that maintains some positive voltage level even in the absence of the input voltage for a certain period of time and a discharge circuit designed to quickly assert the reset signal.
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Patent Agency Ranking
公开(公告)号：US20250112133A1
公开(公告)日：2025-04-03
申请号：US18478087
申请日：2023-09-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Huo Yun DUAN , Tian Sheng CHEN , Hang YAN , Qin PENG , Xiangrui LI
IPC: H01L23/495 , H01L21/56 , H01L23/00 , H01L23/31
Abstract: In examples, a method for manufacturing a package comprises coupling first and second semiconductor dies to a first surface of a conductive terminal; applying a dry film to a second surface of the conductive terminal opposite the first surface; removing a portion of the dry film contacting the second surface to form a dry film opening, the dry film opening having a linear, non-curved edge extending along a width of the conductive terminal; etching the second surface through the dry film opening; removing the dry film; plating the second surface; and sawing through the conductive terminal to form the package.
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公开(公告)号：US20250111096A1
公开(公告)日：2025-04-03
申请号：US18375732
申请日：2023-10-02
Applicant: Texas Instruments Incorporated
Inventor： Veeramanikandan Raju , Anand Kumar G
IPC: G06F21/75
Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to protect against voltage glitch attacks in microcontrollers. An example apparatus includes logic circuitry operable to, in response to a voltage glitch, pause processing circuitry; number generator circuitry operable to generate a number; a counter operable to, after the voltage glitch ends, adjust a count corresponding to the number; and the logic circuitry operable to unpause the processing circuitry after the count reaches a value.
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公开(公告)号：US12267524B2
公开(公告)日：2025-04-01
申请号：US18439181
申请日：2024-02-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Do-Kyoung Kwon , Madhukar Budagavi
IPC: H04N19/567
Abstract: A method for encoding video data is provided that includes determining whether or not a parent coding unit of a coding unit of the video data was predicted in intra-prediction block copy (IntraBC) mode and, when it is determined that the parent coding unit was not predicted in IntraBC mode: computing activity of the coding unit, determining an IntraBC coding cost of the coding unit by computing the IntraBC coding cost of the coding unit using a two dimensional (2D) search when the activity of the coding unit is not than an activity threshold, and computing the IntraBC coding cost of the coding unit using a one dimensional (1D) search when the activity of the coding unit is less than the activity threshold, using the IntraBC coding cost to select an encoding mode from one of a plurality of encoding modes, encoding the coding unit using the selected encoding mode.
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公开(公告)号：US12267182B2
公开(公告)日：2025-04-01
申请号：US18117511
申请日：2023-03-06
Applicant: Texas Instruments Incorporated
Inventor： Raghu Ganesan , Saravanakkumar Radhakrishnan , Gaurav Aggarwal
Abstract: A receiver circuit includes a feedback loop including a device. The receiver circuit also includes a register and a sequencer. The sequencer is configured to, responsive to an error signal being below a threshold value, cause the register to store a value indicative of the state of the feedback loop. The sequencer is also configured to cause the feedback loop to transition to a lower power state, and, responsive to a detected wake-up event, cause the previously stored value indicative of the state of the feedback loop to be loaded from the register into the device and enable the feedback loop.
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公开(公告)号：US12266624B2
公开(公告)日：2025-04-01
申请号：US17488715
申请日：2021-09-29
Applicant: Texas Instruments Incorporated
Inventor： John Carlo Cruz Molina , Rafael Jose Lizares Guevara
Abstract: A semiconductor die includes a semiconductor surface including circuitry electrically connected to top-level bond pads exposed on a top surface of the semiconductor die, the top-level bond pads including inner bond pads and outer bond pads positioned beyond the inner bond pads. There is solder on at least the inner bond pads. A ring structure is positioned around a location of at least the inner bond pads.
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