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    SEMICONDUCTOR PACKAGE STRUCTURE AND SEMICONDUCTOR PROCESS
    42.
    发明申请
    SEMICONDUCTOR PACKAGE STRUCTURE AND SEMICONDUCTOR PROCESS 审中-公开

    公开(公告)号：US20160322292A1

    公开(公告)日：2016-11-03

    申请号：US15208569

    申请日：2016-07-12

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Yuan-Chang SU ,  Chih-Cheng LEE ,  Cheng-Lin HO

    IPC: H01L23/498

    CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K1/188 ,  H01L2924/00

    Abstract: Disclosed is a semiconductor package structure and manufacturing method. The semiconductor package structure includes a first dielectric layer, a second dielectric layer, a component, a patterned conductive layer and at least two conductive vias. The first dielectric layer has a first surface and a second surface opposite the first surface. The second dielectric layer has a first surface and a second surface opposite the first surface. The second surface of the first dielectric layer is attached to the first surface of the second dielectric layer. A component within the second dielectric layer has at least two electrical contacts adjacent to the second surface of the first dielectric layer. The patterned conductive layer within the first dielectric layer is adjacent to the first surface of the first dielectric layer. The conductive vias penetrate the first dielectric layer and electrically connect the electrical contacts with the patterned conductive layer.

    SEMICONDUCTOR SUBSTRATE STRUCTURE, SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
    43.
    发明申请
    SEMICONDUCTOR SUBSTRATE STRUCTURE, SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    半导体衬底结构，半导体封装及其制造方法

    公开(公告)号：US20160240462A1

    公开(公告)日：2016-08-18

    申请号：US14624388

    申请日：2015-02-17

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Tien-Szu CHEN ,  Kuang-Hsiung CHEN ,  Sheng-Ming WANG ,  Yu-Ying LEE ,  Li-Chuan TSAI ,  Chih-Cheng LEE

    IPC: H01L23/498 ,  H01L21/48

    CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

    Abstract: The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure, a dielectric structure and a metal bump. The conductive structure has a first conductive surface and a second conductive surface. The dielectric structure has a first dielectric surface and a second dielectric surface. The first conductive surface does not protrude from the first dielectric surface. The second conductive surface is recessed from the second dielectric surface. The metal bump is disposed in a dielectric opening of the dielectric structure, and is physically and electrically connected to the second conductive surface. The metal bump has a concave surface.

    Abstract translation: 本公开涉及一种半导体衬底结构，半导体封装及其制造方法。 半导体衬底结构包括导电结构，电介质结构和金属凸块。 导电结构具有第一导电表面和第二导电表面。 电介质结构具有第一电介质表面和第二电介质表面。 第一导电表面不从第一电介质表面突出。 第二导电表面从第二电介质表面凹陷。 金属凸块设置在电介质结构的电介质开口中，并且物理地和电连接到第二导电表面。 金属凸块具有凹面。

    SEMICONDUCTOR PACKAGE INCLUDING EMBEDDED COMPONENTS AND METHOD OF MAKING THE SAME
    44.
    发明申请
    SEMICONDUCTOR PACKAGE INCLUDING EMBEDDED COMPONENTS AND METHOD OF MAKING THE SAME 审中-公开
    半导体封装包括嵌入式元件及其制造方法

    公开(公告)号：US20160133562A1

    公开(公告)日：2016-05-12

    申请号：US14703794

    申请日：2015-05-04

    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

    Inventor： Chih-Cheng LEE ,  Yuan-Chang SU ,  Yu-Lin SHIH ,  You-Lung Yen

    IPC: H01L23/522 ,  H01L21/768 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/532

    CPC classification number: H01L21/481 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/92144

    Abstract: The present disclosure relates to a semiconductor package and method of making the same. The semiconductor package includes an encapsulation layer, a component within the encapsulation layer, a first dielectric layer, a second dielectric layer, a first patterned conductive layer, and a second patterned conductive layer. The component includes pads on a front surface of the component. The first dielectric layer is disposed on a surface of the encapsulation layer. The second dielectric layer is disposed on a surface of the first dielectric layer. The first and second dielectric layers define via holes extending from the second dielectric layer to respective ones of the pads. The first patterned conductive layer is disposed within the first dielectric layer and surrounds the via holes. The second patterned conductive layer is disposed within the second dielectric layer and surrounds the via holes.

    Abstract translation: 本公开涉及一种半导体封装及其制造方法。 半导体封装包括封装层，封装层内的部件，第一介电层，第二介电层，第一图案化导电层和第二图案化导电层。 该部件包括在该部件的前表面上的焊盘。 第一介电层设置在封装层的表面上。 第二电介质层设置在第一电介质层的表面上。 第一和第二电介质层限定了从第二电介质层延伸到各个焊盘的通孔。 第一图案化导电层设置在第一介电层内并包围通孔。 第二图案化导电层设置在第二介电层内并包围通孔。

    SUBSTRATE, SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    48.
    发明公开
    SUBSTRATE, SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20240030120A1

    公开(公告)日：2024-01-25

    申请号：US18375140

    申请日：2023-09-29

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Cheng-Lin HO ,  Chih-Cheng LEE

    IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48

    CPC classification number: H01L23/49827 ,  H01L23/3157 ,  H01L21/4857 ,  H01L23/49816 ,  H01L21/486 ,  H01L23/49822

    Abstract: A substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface disposed adjacent to the first surface of the first dielectric layer. The substrate further includes a first conductive via disposed in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite the first end. The substrate further includes a second conductive via disposed in the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer. A width of the first end of the first conductive via is smaller than a width of the second end of the first conductive via, and a width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via.

    ELECTRONIC PACKAGE
    50.
    发明申请
    ELECTRONIC PACKAGE 有权

    公开(公告)号：US20230061843A1

    公开(公告)日：2023-03-02

    申请号：US17460053

    申请日：2021-08-27

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Yu-Lin SHIH ,  Chih-Cheng LEE

    IPC: H01L23/498 ,  H01L23/31

    Abstract: An electronic package is provided. The electronic package includes a first circuit structure, a second circuit structure, and an underfill. The second circuit structure is disposed over the first circuit structure. The underfill is disposed between the first circuit structure and the second circuit structure. An inner portion of the underfill has an inner lateral surface adjacent to and is substantially conformal with a lateral surface of the second circuit structure. A first top end of the inner lateral surface is not level with a top surface of the second circuit structure. An outer portion of the underfill has a second top end higher than the first top end.

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