公开(公告)号：US20060118425A1

公开(公告)日：2006-06-08

申请号：US11343477

申请日：2006-01-30

Applicant: Bulent Basol ,  Cyprian Uzoh ,  Homayoun Talieh

Inventor： Bulent Basol ,  Cyprian Uzoh ,  Homayoun Talieh

IPC: C25D5/02

CPC classification number: C25D5/022 ,  C25D5/18 ,  C25D5/22 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/32125 ,  H01L21/7684 ,  H01L21/76877

Abstract: A layer structure usable in manufacturing an integrated circuit is made, in a single apparatus, by a particular process in which a patterned substrate is provided. An electrolyte solution, out of which a conductive material can be plated under an applied potential, is supplied over a surface of the patterned substrate, and a potential is applied so as to deposit a film of the conductive material out of the electrolyte solution and over the surface of the patterned substrate. The film of conductive material is preferably polished as it is deposited. The conductive material is then removed from field regions of the patterned substrate, while deposits of the conductive material are left in features defined in the patterned substrate. The deposits of the conductive material are then electrically isolated, resulting in the layer structure.

Abstract translation: 在单一设备中，通过提供图案化衬底的特定工艺制造可用于制造集成电路的层结构。 在图案化衬底的表面上提供电解质溶液，其中可以在施加电位下电镀导电材料，并且施加电位以将导电材料的膜从电解质溶液中沉积出来并且越过 图案化衬底的表面。 导电材料的膜优选在其沉积时被抛光。 导电材料然后从图案化衬底的场区域移除，而导电材料的沉积物留在图案化衬底中限定的特征中。 然后导电材料的沉积物被电隔离，导致层结构。

公开(公告)号：US20060017169A1

公开(公告)日：2006-01-26

申请号：US11168559

申请日：2005-06-29

Applicant: Panayotis Andricacos ,  Hariklia Deligianni ,  John Dukovic ,  Daniel Edelstein ,  Wilma Horkans ,  Chao-Kun Hu ,  Jeffrey Hurd ,  Kenneth Rodbell ,  Cyprian Uzoh ,  Kwong-Hon Wong

Inventor： Panayotis Andricacos ,  Hariklia Deligianni ,  John Dukovic ,  Daniel Edelstein ,  Wilma Horkans ,  Chao-Kun Hu ,  Jeffrey Hurd ,  Kenneth Rodbell ,  Cyprian Uzoh ,  Kwong-Hon Wong

IPC: H01L23/48 ,  H01L21/44

CPC classification number: C25D3/38 ,  C25D5/022 ,  H01L21/2885 ,  H01L21/76877 ,  H01L21/76885

Abstract: A process is described for the fabrication of submicton interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of CU electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.

Abstract translation: 描述了用于集成电路芯片的亚微米互连结构的制造的过程。 通过从包含添加剂的浴中电镀Cu获得无空隙和无缝导体，并且通常用于沉积水平，光亮，延展性和低应力Cu金属。 这种方法在不留下空隙或接缝的情况下超滤特征的能力是独一无二的，优于其他沉积方法。 以这种方式电镀Cu的结构的电迁移阻力优于AlCu结构或使用不是电镀方法沉积的Cu制造的结构的电迁移电阻。

公开(公告)号：US20050095854A1

公开(公告)日：2005-05-05

申请号：US10698878

申请日：2003-10-31

Applicant: Cyprian Uzoh ,  Bulent Basol

Inventor： Cyprian Uzoh ,  Bulent Basol

IPC: H01L21/288 ,  H01L21/768 ,  H01L21/44

CPC classification number: H01L21/76877 ,  H01L21/2885

Abstract: A process of electrodepositing a substantially flat conductive layer on a workpiece surface is provided. In the process, various transition current densities are determined experimentally by evaluating the effects of the plating current density on gap fill profile in the smallest cavities with the largest tendency to over-plate on the substrate. After determining the transition currents on experimental wafers or dies, an electrochemical plating process is performed to apply selected transition current densities as process current densities to form a substantially flat profile over the smallest cavities.

Abstract translation: 提供了在工件表面上电沉积基本平坦的导电层的工艺。 在此过程中，通过评估电镀电流密度对最小空腔中的间隙填充轮廓的影响，在基板上具有最大的过平板倾向，实验确定了各种转变电流密度。 在确定实验晶片或裸片上的转换电流之后，执行电化学电镀工艺以将所选择的过渡电流密度用作过程电流密度，以在最小空腔上形成基本平坦的轮廓。

公开(公告)号：US20050079713A1

公开(公告)日：2005-04-14

申请号：US10920028

申请日：2004-08-16

Applicant: Jalal Ashjaee ,  Rimma Volodarsky ,  Cyprian Uzoh ,  Bulent Basol ,  Homayoun Talieh

Inventor： Jalal Ashjaee ,  Rimma Volodarsky ,  Cyprian Uzoh ,  Bulent Basol ,  Homayoun Talieh

IPC: H01L21/00 ,  H01L21/288 ,  H01L21/3213 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/6708 ,  H01L21/2885 ,  H01L21/32134

Abstract: The present invention provides at least one nozzle that sprays a rotating workpiece with an etchant at an edge thereof. The at least one nozzle is located in an upper chamber of a vertically configured processing subsystem that also includes mechanisms for plating, cleaning and drying in upper and lower chambers

Abstract translation: 本发明提供了至少一个喷嘴，其在其边缘处用蚀刻剂喷射旋转的工件。 所述至少一个喷嘴位于垂直构造的处理子系统的上腔室中，所述处理子系统还包括用于在上腔室和下室中进行电镀，清洁和干燥的机构

公开(公告)号：US20050034976A1

公开(公告)日：2005-02-17

申请号：US10946703

申请日：2004-09-21

Applicant: Homayoun Talieh ,  Cyprian Uzoh

Inventor： Homayoun Talieh ,  Cyprian Uzoh

IPC: B24B37/16 ,  C25D5/06 ,  C25D5/22 ,  C25D7/12 ,  C25D17/00 ,  C25D17/12 ,  C25D17/14 ,  C25F7/00 ,  H01L21/288 ,  H01L21/304 ,  H01L21/3205 ,  H01L21/321 ,  C25D5/48

CPC classification number: B24B37/16 ,  C25D5/06 ,  C25D5/22 ,  C25D7/123 ,  C25D17/001 ,  C25D17/14 ,  C25F7/00 ,  H01L21/3212

Abstract: The present invention provides a method and apparatus that plates/deposits a conductive material on a semiconductor substrate and then polishes the same substrate. This is achieved by providing multiple chambers in a single apparatus, where one chamber can be used for plating/depositing the conductive material and another chamber can be used for polishing the semiconductor substrate. The plating/depositing process can be performed using brush plating or electro chemical mechanical deposition and the polishing process can be performed using electropolishing or chemical mechanical polishing. The present invention further provides a method and apparatus for intermittently applying the conductive material to the semiconductor substrate and also intermittently polishing the substrate when such conductive material is not being applied to the substrate. Furthermore, the present invention provides a method and apparatus that plates/deposits and/or polishes a conductive material and improves the electrolyte mass transfer properties on a substrate using a novel anode assembly.

Abstract translation: 本发明提供一种在半导体衬底上沉积/沉积导电材料然后抛光相同衬底的方法和装置。 这通过在单个设备中提供多个室来实现，其中一个室可以用于电镀/沉积导电材料，并且另一个室可以用于抛光半导体衬底。 电镀/沉积工艺可以使用刷镀或电化学机械沉积进行，并且可以使用电抛光或化学机械抛光进行抛光工艺。 本发明还提供一种用于将导电材料间歇地施加到半导体衬底的方法和装置，并且当这种导电材料未被施加到衬底时也间歇地抛光衬底。 此外，本发明提供了一种使用新型阳极组件对导电材料进行平板/沉积和/或抛光并改善基板上的电解质传质性质的方法和装置。

公开(公告)号：US09125333B2

公开(公告)日：2015-09-01

申请号：US13183870

申请日：2011-07-15

Applicant: Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed ,  Belgacem Haba ,  Piyush Savalia ,  Craig Mitchell

Inventor： Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed ,  Belgacem Haba ,  Piyush Savalia ,  Craig Mitchell

IPC: H05K1/03 ,  H05K1/09 ,  H05K3/40

CPC classification number: H01L24/05 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05169 ,  H01L2224/056 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/013 ,  H05K1/09 ,  H05K3/4007 ,  H05K2201/032 ,  H05K2201/0326 ,  H05K2201/0338

Abstract: Barrier layers for use in electrical applications. In some embodiments the barrier layer is a laminated barrier layer. In some embodiments the barrier layer includes a graded barrier layer.

Abstract translation: 用于电气应用的阻隔层。 在一些实施例中，阻挡层是层压阻挡层。 在一些实施例中，阻挡层包括梯度阻挡层。

公开(公告)号：US20130122747A1

公开(公告)日：2013-05-16

申请号：US13296785

申请日：2011-11-15

Applicant: Cyprian Uzoh ,  Craig Mitchell ,  Belgacem Haba ,  Ilyas Mohammed

Inventor： Cyprian Uzoh ,  Craig Mitchell ,  Belgacem Haba ,  Ilyas Mohammed

IPC: H01R24/28

CPC classification number: H05K1/0271 ,  H01L23/49827 ,  H01L2924/0002 ,  H01R12/714 ,  H05K1/114 ,  H05K1/115 ,  H05K3/42 ,  H05K2201/09645 ,  H05K2201/10378 ,  H05K2203/0242 ,  H05K2203/025 ,  Y10T29/49165 ,  H01L2924/00

Abstract: An interconnection component includes an element with an opening, a plurality of conductors electrically insulted from one another extending through the opening, and a plurality of second contacts electrically insulated from one another. The element is comprised of a material having a coefficient of thermal expansion of less than 10 parts per million per degree Celsius. At least some of the conductors extend along at least one inner surface of the opening. The conductors define a plurality of wettable first contacts at the first surface. The first contacts are at least partially aligned with the opening in a direction of the thickness and electrically insulated from one another.

Abstract translation: 互连部件包括具有开口的元件，延伸穿过开口彼此电绝缘的多个导体以及彼此电绝缘的多个第二触点。 该元件由热膨胀系数小于10ppm /℃的材料构成。 至少一些导体沿开口的至少一个内表面延伸。 导体在第一表面限定多个可润湿的第一接触。 第一触点在厚度方向上与开口至少部分地对齐，并且彼此电绝缘。

公开(公告)号：US20130118784A1

公开(公告)日：2013-05-16

申请号：US13293698

申请日：2011-11-10

Applicant: Cyprian Uzoh ,  Charles G. Woychik ,  Terrence Caskey ,  Belgacem Haba ,  Philip Damberg

Inventor： Cyprian Uzoh ,  Charles G. Woychik ,  Terrence Caskey ,  Belgacem Haba ,  Philip Damberg

IPC: H05K1/09 ,  H05K3/10

CPC classification number: H05K1/115 ,  H01L23/14 ,  H01L23/49827 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K1/03 ,  H05K1/09 ,  H05K3/42 ,  H05K2201/0141 ,  H05K2201/0175 ,  H05K2201/09509 ,  H05K2201/10378 ,  H05K2203/025 ,  H05K2203/1105 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A component includes a support structure having first and second spaced-apart and parallel surfaces and a plurality of conductive elements extending in a direction between the first and second surfaces. Each conductive element contains an alloy of a wiring metal selected from the group consisting of copper, aluminum, nickel and chromium, and an additive selected from the group consisting of Gallium, Germanium, Indium, Selenium, Tin, Sulfur, Silver, Phosphorus, and Bismuth. The alloy has a composition that varies with distance in at least one direction across the conductive element. A concentration of the additive is less than or equal to 5% of the total atomic mass of the conductive element, and a resistivity of the conductive element is between 2.5 and 30 micro-ohm-centimeter.

公开(公告)号：US20130014979A1

公开(公告)日：2013-01-17

申请号：US13183920

申请日：2011-07-15

Applicant: Cyprian Uzoh ,  Craig Mitchell

Inventor： Cyprian Uzoh ,  Craig Mitchell

IPC: H05K1/09 ,  H05K3/10 ,  H05K1/00

CPC classification number: H01R13/03 ,  H05K1/09 ,  H05K3/282 ,  H05K3/4007 ,  H05K2201/0338 ,  H05K2201/09745 ,  Y10T29/49155

Abstract: Electrical contacts comprising a surface with a plurality of cavities therein and their methods of manufacture and use.

Abstract translation: 电触头包括其中具有多个空腔的表面及其制造和使用方法。

公开(公告)号：US20120326326A1

公开(公告)日：2012-12-27

申请号：US13168839

申请日：2011-06-24

Applicant: Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed

Inventor： Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/3212 ,  H01L21/32125 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/7688 ,  H01L23/481 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a co-planar or flat top surface. Another feature is a method of forming an interconnect structure that results in the interconnect structure having a surface that is angled upwards greater than zero with respect to a top surface of the substrate. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

Abstract translation: 提供了用于形成半导体器件的方法和装置，其可以包括任何数量的特征。 一个特征是形成互连结构的方法，其导致互连结构具有共面或平坦的顶表面。 另一个特征是形成互连结构的方法，其导致互连结构具有相对于衬底顶表面向上倾斜大于零的表面。 互连结构可以包括镶嵌结构，例如单镶嵌结构或双镶嵌结构，或者可以包括硅通孔（TSV）结构。