公开(公告)号：US08952545B2

公开(公告)日：2015-02-10

申请号：US13965630

申请日：2013-08-13

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Henrik Ewe ,  Klaus Schiess ,  Manfred Mengel

IPC: H01L23/48 ,  H01L23/36 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L21/50

CPC classification number: H01L23/481 ,  H01L21/50 ,  H01L23/36 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/25 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/82102 ,  H01L2224/92144 ,  H01L2224/9222 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01327 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/00

Abstract: One aspect is a device including a carrier comprising a first conducting layer, a first insulating layer over the first conducting layer, and at least one first through-connection from a first face of the first insulating layer to a second face of the first insulating layer. A semiconductor chip is attached to the carrier and a second insulating layer is over the carrier and the semiconductor chip. A metal layer is over the second insulating layer. A second through-connection is through the second insulating layer electrically coupling the semiconductor chip to the metal layer. A third through-connection is through the second insulating layer electrically coupling the carrier to the metal layer.

Abstract translation: 一个方面是包括载体的器件，其包括第一导电层，在第一导电层上的第一绝缘层，以及从第一绝缘层的第一面到第一绝缘层的第二面的至少一个第一通孔连接 。 半导体芯片附着到载体上，第二绝缘层位于载体和半导体芯片之上。 金属层在第二绝缘层之上。 第二直通连接通过第二绝缘层将半导体芯片电耦合到金属层。 第三直通连接是通过第二绝缘层将载体电耦合到金属层。

公开(公告)号：US08853835B2

公开(公告)日：2014-10-07

申请号：US13645548

申请日：2012-10-05

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Gerhard Noebauer ,  Chooi Mei Chong

IPC: H01L23/495

CPC classification number: H01L23/495 ,  H01L23/488 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/03 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/84 ,  H01L24/92 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/29298 ,  H01L2224/32245 ,  H01L2224/37111 ,  H01L2224/37118 ,  H01L2224/37124 ,  H01L2224/37139 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/37155 ,  H01L2224/3716 ,  H01L2224/37164 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49112 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8382 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/0781 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15701 ,  H01L2924/15717 ,  H01L2924/15724 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/15763 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/45099

Abstract: A chip package is provided. The chip package includes a chip carrier, a voltage supply lead, a sensing terminal and a chip disposed over the chip carrier. The chip includes a first terminal and a second terminal, wherein the first terminal electrically contacts the chip carrier. The chip package also includes an electrically conductive element formed over the second terminal, the electrically conductive element electrically coupling the second terminal to the voltage supply lead and the sensing terminal.

Abstract translation: 提供芯片封装。 芯片封装包括芯片载体，电压源引线，感测端子和设置在芯片载体上的芯片。 芯片包括第一端子和第二端子，其中第一端子电接触芯片载体。 芯片封装还包括形成在第二端子上的导电元件，导电元件将第二端子电耦合到电压源引线和感测端子。

公开(公告)号：US20140197552A1

公开(公告)日：2014-07-17

申请号：US13742456

申请日：2013-01-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Xaver Schloegel ,  Wolfram Hable ,  Manfred Mengel ,  Joachim Mahler ,  Khalil Hosseini ,  Franz-Peter Kalz

IPC: H01L23/29 ,  H01L21/56

CPC classification number: H01L23/29 ,  H01L21/56 ,  H01L23/06 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A chip arrangement is provided, the chip arrangement, including a carrier; at least one chip electrically connected to a carrier top side; an encapsulation material at least partially surrounding the at least one chip and the carrier top side, wherein the encapsulation material is formed on one or more lateral sides of the carrier; and a ceramic material disposed on a carrier bottom side, and on at least one side of the encapsulation material.

Abstract translation: 提供了芯片布置，芯片布置包括载体; 至少一个芯片电连接到载体顶侧; 至少部分地围绕所述至少一个芯片和所述载体顶侧的封装材料，其中所述封装材料形成在所述载体的一个或多个侧面上; 以及设置在载体底侧上的至少一个侧面上的陶瓷材料。

公开(公告)号：US20130143368A1

公开(公告)日：2013-06-06

申请号：US13722231

申请日：2012-12-20

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba

IPC: H01L21/56

CPC classification number: H01L21/565 ,  H01L23/3121 ,  H01L23/49805 ,  H01L24/48 ,  H01L2224/16105 ,  H01L2224/32105 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2924/00014 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A module including a carrier and a semiconductor chip applied to the carrier. An external contact element is provided having a first portion and a second portion extending perpendicular to the first portion, wherein a thickness of the second portion is smaller than a thickness of the carrier.

公开(公告)号：US11942383B2

公开(公告)日：2024-03-26

申请号：US17501568

申请日：2021-10-14

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Chii Shang Hong ,  Teck Sim Lee ,  Ralf Otremba ,  Daniel Pedone ,  Bernd Schmoelzer

IPC: H01L23/16 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367

CPC classification number: H01L23/16 ,  H01L21/4871 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3672

Abstract: A package for mounting on a mounting base is disclosed. In one example, the package comprises a carrier, an electronic component mounted at the carrier, leads electrically coupled with the electronic component and to be electrically coupled with the mounting base, and a linear spacer for defining a spacing with respect to the carrier.

公开(公告)号：US20240087995A1

公开(公告)日：2024-03-14

申请号：US18453639

申请日：2023-08-22

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Thai Kee Gan ,  Teck Sim Lee ,  Chwee Pang Tommy Khoo ,  Christian Schiele ,  Katrin Unterhofer ,  Patrick Uredat

IPC: H01L23/495 ,  H01L23/00 ,  H01L25/00 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L23/49555 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/48 ,  H01L25/072 ,  H01L25/18 ,  H01L25/50 ,  H01L24/49 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/4903

Abstract: A power semiconductor package includes: a die carrier having first and second opposite sides; and first and second power semiconductor dies each having first and second power electrodes on opposite sides. The second power electrodes face and are electrically coupled to the first side of the carrier. A molded body at least partially encapsulates the dies and has a first and second opposite sides and lateral sides connecting the first and second sides. First and second power contacts and first and second control contacts are arranged laterally next to each other. The first power electrode of the first die is electrically coupled to the first power contact by a first electrical connector. The first power electrode of the second die is electrically coupled to the second power contact by a second electrical connector. A width of each power contact is at least four times the width of each control contact.

公开(公告)号：US11676881B2

公开(公告)日：2023-06-13

申请号：US16929223

申请日：2020-07-15

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Teck Sim Lee ,  Klaus Schiess ,  Xaver Schloegel ,  Lee Shuang Wang ,  Mohd Hasrul Zulkifli

IPC: H01L23/367 ,  H01L23/12 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/3677 ,  H01L21/4871 ,  H01L23/12 ,  H01L23/3107

Abstract: A semiconductor package is disclosed. In one example, the semiconductor package includes a chip carrier, a semiconductor chip attached to the chip carrier, an encapsulation body encapsulating the semiconductor chip, and a mounting hole configured to receive a screw for screw mounting a heatsink onto a first side of the semiconductor package. A second side of the semiconductor package opposite the first side is configured to be surface mounted to an application board.

公开(公告)号：US20230079413A1

公开(公告)日：2023-03-16

申请号：US17473423

申请日：2021-09-13

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba

IPC: H01L23/473 ,  H01L25/07

Abstract: A semiconductor device assembly includes a cooling system, a plurality of semiconductor packages, each including a semiconductor die and an encapsulant body, and a multi-device thermal interface interposed between the plurality of semiconductor packages and the cooling system, wherein the semiconductor packages are each configured as surface mount devices, and wherein the multi-device thermal interface thermally couples each of the semiconductor packages to the cooling system.

公开(公告)号：US20220173006A1

公开(公告)日：2022-06-02

申请号：US17531867

申请日：2021-11-22

Applicant: Infineon Technologies AG

Inventor： Thai Kee Gan ,  Sanjay Kumar Murugan ,  Ralf Otremba

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29

Abstract: A chip package including a semiconductor chip is provided. The chip package may include a packaging material at least partially around the semiconductor chip with an opening extending from a top surface of the packaging material to the semiconductor chip and/or to an electrical contact structure contacting the semiconductor chip, and a thermally conductive material in the opening, wherein the thermally conductive material is configured to transfer heat from the semiconductor chip to an outside, wherein the thermally conductive material extends laterally at least partially over the top surface of the packaging material.

公开(公告)号：US11329000B2

公开(公告)日：2022-05-10

申请号：US16798536

申请日：2020-02-24

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba

IPC: H01L23/31 ,  H01L23/538 ,  H01L21/50 ,  H01L23/42 ,  H01L25/07 ,  H01L21/60

Abstract: A package includes: a package body having an outside housing including first and second package sides and package sidewalls that extend between the first and second package sides; first and second electrically conductive interface layers spaced apart from each other at the outside housing; and first and second power semiconductor chips arranged within the package body, both chips having a respective first load terminal and a respective second load terminal. The first load terminals are electrically connected to each other within the package body. The second load terminal of the first chip is electrically connected to the first electrically conductive interface layer. The second load terminal of the second chip is electrically connected to the second electrically conductive interface layer. The outside housing of the package body further includes a creepage structure having a minimum dimension between the first electrically conductive interface layer and the second electrically conductive interface layer.