公开(公告)号：US11991873B2

公开(公告)日：2024-05-21

申请号：US18109780

申请日：2023-02-14

Applicant: Intel Corporation

Inventor： Travis W. Lajoie ,  Abhishek A. Sharma ,  Van H. Le ,  Chieh-Jen Ku ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani ,  Gregory George ,  Akash Garg ,  Julie Rollins ,  Allen B. Gardiner ,  Shem Ogadhoh ,  Juan G. Alzate Vinasco ,  Umut Arslan ,  Fatih Hamzaoglu ,  Nikhil Mehta ,  Yu-Wen Huang ,  Shu Zhou

IPC: H10B12/00

CPC classification number: H10B12/03 ,  H10B12/05 ,  H10B12/30

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.

公开(公告)号：US11784257B2

公开(公告)日：2023-10-10

申请号：US17475196

申请日：2021-09-14

Applicant: Intel Corporation

Inventor： Bernhard Sell

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/786 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L27/12 ,  H01L27/092 ,  H10B12/00 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/16 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/7853 ,  H01L21/02532 ,  H01L21/3083 ,  H01L21/30604 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/786 ,  H01L29/7851 ,  H01L29/7854 ,  H01L29/7856 ,  H10B12/056 ,  H10B12/36 ,  H01L2924/13067

Abstract: Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.

公开(公告)号：US11728335B2

公开(公告)日：2023-08-15

申请号：US16257855

申请日：2019-01-25

Applicant: Intel Corporation

Inventor： Guannan Liu ,  Akm A. Ahsan ,  Mark Armstrong ,  Bernhard Sell

IPC: H01L27/07 ,  H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L29/08 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/0705 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, buried channel structures integrated with non-planar structures. In an example, an integrated circuit structure includes a first fin structure and a second fin structure above a substrate. A gate structure is on a portion of the substrate directly between the first fin structure and the second fin structure. A source region is in the first fin structure. A drain region is in the second fin structure.

公开(公告)号：US20230067765A1

公开(公告)日：2023-03-02

申请号：US17409877

申请日：2021-08-24

Applicant: INTEL CORPORATION

Inventor： Abhishek A. Sharma ,  Noriyuki Sato ,  Van H. Le ,  Sarah Atanasov ,  Hui Jae Yoo ,  Bernhard Sell ,  Pei-hua Wang ,  Travis W. Lajoie ,  Chieh-Jen Ku ,  Juan G. Alzate-Vinasco ,  Fatih Hamzaoglu

IPC: H01L23/00 ,  H01L25/065

Abstract: IC devices implementing bilayer stacking with lines shared between bottom and top memory layers, and associated systems and methods, are disclosed. An example IC device includes a support structure, a front end of line (FEOL) layer and a back end of line (BEOL) layer. The BEOL layer includes a first memory cell in a first layer over the support structure, an electrically conductive line in a second layer, above the first layer, and a second memory cell in a third layer, above the second layer. The line could be one of a wordline, a bitline, or a plateline that is shared between the first and second memory cells. In particular, bilayer stacking line sharing is such that only one line is provided as a line to be shared between one or more of the memory cells of the first layer and one or more memory cells of the third layer.

公开(公告)号：US20220415897A1

公开(公告)日：2022-12-29

申请号：US17358954

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Juan G. Alzate-Vinasco ,  Travis W. LaJoie ,  Elliot N. Tan ,  Kimberly Pierce ,  Shem Ogadhoh ,  Abhishek A. Sharma ,  Bernhard Sell ,  Pei-Hua Wang ,  Chieh-Jen Ku

IPC: H01L27/108 ,  H01L29/786 ,  H01L29/66

Abstract: A device structure includes a first interconnect line along a longitudinal direction and a second interconnect line parallel to the first interconnect line, where the first interconnect structure is within a first metallization level and the second interconnect line is within a second metallization level. A first transistor and a laterally separated second transistor are on a same plane above the second interconnect line, where a gate of the first transistor is coupled to the first interconnect line and a gate of the second transistor is coupled to the second interconnect line. A first capacitor is coupled to a first terminal of the first transistor and a second capacitor is coupled to a first terminal of the second transistor. A third interconnect line couples a second terminal of the first transistor with a second terminal of the second transistor.

公开(公告)号：US20220415573A1

公开(公告)日：2022-12-29

申请号：US17357385

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： James D. Waldemer ,  Matthieu Giraud-Carrier ,  Bernhard Sell ,  Travis W. Lajoie ,  Wilfred Gomes ,  Abhishek A. Sharma

IPC: H01G4/005 ,  H01G4/30 ,  H01G4/40

Abstract: Disclosed herein are IC structures with three-dimensional capacitors with double metal electrodes provided in a support structure (e.g., a substrate, a die, a wafer, or a chip). An example three-dimensional capacitor includes first and second capacitor electrodes and a capacitor insulator between them. Each capacitor electrode includes a planar portion extending across the support structure and one or more via portions extending into one or more via openings in the support structure. The capacitor insulator also includes a planar portion and a via portion extending into the via opening(s). The planar portion of the capacitor electrodes are thicker than the via portions. Each capacitor electrode may be deposited using two deposition processes, such as a conformal deposition process for depositing the via portion of the electrode, and a sputter process for depositing the planar portion of the electrode.

公开(公告)号：US20220189913A1

公开(公告)日：2022-06-16

申请号：US17117350

申请日：2020-12-10

Applicant: Intel Corporation

Inventor： Sarah Atanasov ,  Abhishek A. Sharma ,  Bernhard Sell ,  Chieh-Jen Ku ,  Elliot Tan ,  Hui Jae Yoo ,  Noriyuki Sato ,  Travis W. Lajoie ,  Van H. Le ,  Thoe Michaelos

IPC: H01L25/065 ,  H01L27/108

Abstract: Disclosed herein are transistors, memory cells, and arrangements thereof. For example, in some embodiments, an integrated circuit (IC) structure may include a plurality of transistors, wherein the transistors are distributed in a hexagonally packed arrangement. In another example, in some embodiments, an IC structure may include a memory cell including an axially symmetric transistor coupled to an axially symmetric capacitor, wherein the axis of the transistor is aligned with the axis of the capacitor.

公开(公告)号：US20220181460A1

公开(公告)日：2022-06-09

申请号：US17114034

申请日：2020-12-07

Applicant: Intel Corporation

Inventor： Chieh-Jen Ku ,  Kendra Souther ,  Andre Baran ,  Pei-hua Wang ,  Bernhard Sell

IPC: H01L29/45 ,  H01L21/443 ,  H01L29/786

Abstract: Disclosed herein are transistor source/drain contacts, and related methods and devices. For example, in some embodiments, a transistor may include a channel and a source/drain contact, wherein the source/drain contact includes an interface material and a bulk material, the bulk material has a different material composition than the interface material, the interface material is between the bulk material and the channel, the interface material includes indium and an element different from indium, and the element is aluminum, vanadium, zirconium, magnesium, gallium, hafnium, silicon, lanthanum, tungsten, or cadmium.

公开(公告)号：US20200035683A1

公开(公告)日：2020-01-30

申请号：US16043548

申请日：2018-07-24

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Juan G. Alzate-Vinasco ,  Fatih Hamzaoglu ,  Bernhard Sell ,  Pei-hua Wang ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani ,  Umut Arslan ,  Travis W. Lajoie ,  Chieh-jen Ku

IPC: H01L27/108 ,  H01L27/06 ,  H01L25/065 ,  H01L29/786 ,  H01L23/00 ,  H01L29/417 ,  G11C11/407 ,  G11C7/06

Abstract: Described herein are arrays of embedded dynamic random-access memory (eDRAM) cells that use TFTs as selector transistors. When at least some selector transistors are implemented as TFTs, different eDRAM cells may be provided in different layers above a substrate, enabling a stacked architecture. An example stacked TFT based eDRAM includes one or more memory cells provided in a first layer over a substrate and one or more memory cells provided in a second layer, above the first layer, where at least the memory cells in the second layer, but preferably the memory cells in both the first and second layers, use TFTs as selector transistors. Stacked TFT based eDRAM allows increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

公开(公告)号：US20190326296A1

公开(公告)日：2019-10-24

申请号：US15956379

申请日：2018-04-18

Applicant: Intel Corporation

Inventor： Yih Wang ,  Abhishek A. Sharma ,  Tahir Ghani ,  Allen B. Gardiner ,  Travis W. Lajoie ,  Pei-hua Wang ,  Chieh-jen Ku ,  Bernhard Sell ,  Juan G. Alzate-Vinasco ,  Blake C. Lin

IPC: H01L27/108 ,  H01L27/12 ,  H01L23/528 ,  H01L23/522 ,  H01L27/06

Abstract: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.