公开(公告)号：US20250006671A1

公开(公告)日：2025-01-02

申请号：US18217123

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Marcel Arlan Wall ,  Hamid Azimi ,  Rahul N. Manepalli ,  Srinivas Venkata Ramanuja Pietambaram ,  Darko Grujicic ,  Steve Cho ,  Thomas L. Sounart ,  Gang Duan ,  Jung Kyu Han ,  Suddhasattwa Nad ,  Benjamin Duong ,  Shayan Kaviani

IPC: H01L23/00

Abstract: An intermediary layer, such as a dry deposition layer or a surface finish, is deposited on at least one exposed surface of surfaces within a layer of a semiconductor substrate. The intermediary layer is deposited on at least an electrically conductive material within a cavity in a layer. The intermediary layer is deposited using a chemical deposition process such as physical vapor deposition, chemical vapor deposition or sputtering.

公开(公告)号：US12159825B2

公开(公告)日：2024-12-03

申请号：US17197531

申请日：2021-03-10

Applicant: Intel Corporation

Inventor： Rahul Manepalli ,  Suddhasattwa Nad ,  Marcel Wall ,  Darko Grujicic

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

Abstract: An electronic substrate may be formed having at least one metal-to-dielectric adhesion promotion material layer therein. The electronic substrate may comprise a conductive metal trace, a dielectric material layer on the conductive metal trace, and the adhesion promotion material layer between the conductive metal trace and the dielectric material layer, wherein the adhesion promotion material layer comprises an organic adhesion material and a metal constituent dispersed within the organic adhesion material, wherein a metal within the metal constituent has a standard reduction potential greater than a standard reduction potential of the conductive metal trace.

公开(公告)号：US20240321657A1

公开(公告)日：2024-09-26

申请号：US18189782

申请日：2023-03-24

Applicant: Intel Corporation

Inventor： Darko Grujicic ,  Suddhasattwa Nad ,  Srinivas Pietambaram ,  Rengarajan Shanmugam ,  Marcel Wall ,  Sashi Kandanur ,  Rahul Manepalli ,  Robert May

IPC: H01L23/15 ,  H01L23/498

CPC classification number: H01L23/15 ,  H01L23/49827 ,  H01L23/49866 ,  G02B6/4214

Abstract: Photonic integrated circuit packages and methods of manufacturing are disclosed. An example integrated circuit package includes: a semiconductor die; a package substrate supporting the semiconductor die, the package substrate including a glass core, the glass core including a through glass via extending between opposing first and second surfaces of the glass core, the glass core including a recess spaced apart from the through glass via, the recess defined by a third surface of the glass core, the recess having a different shape than the through glass via; and a reflective metal disposed on the third surface to define a mirror, the reflective metal also disposed between a wall of the through glass via and a conductive material disposed in the through glass via.

公开(公告)号：US20240224543A1

公开(公告)日：2024-07-04

申请号：US18091264

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Gang Duan ,  Srinivas Pietambaram ,  Brandon Marin ,  Jeremy Ecton

IPC: H10B80/00 ,  H01L21/48 ,  H01L23/15 ,  H01L23/498

CPC classification number: H10B80/00 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49827

Abstract: Multi-chip/die device including a logic IC die facing a first side of a glass substrate and a memory IC die facing, and coupled to, the logic IC die. First ones of first metallization features of the logic IC die are coupled to through-glass vias extending through a thickness of the glass substrate. The memory IC die is coupled to second ones of the first metallization features, either directly or by way of other through-glass vias. The logic IC die and/or memory IC die may be directly bonded to the through-glass vias or may be attached by solder. The logic IC die or memory IC die may be embedded within the glass substrate. Through-glass vias within a region beyond an edge of the memory IC die may couple the logic IC die to a host component either through a routing structure built up adjacent the memory IC die, or through solder features attached to the glass substrate adjacent to the memory IC die.

公开(公告)号：US20240222298A1

公开(公告)日：2024-07-04

申请号：US18091583

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Brandon Christian Marin ,  Srinivas V. Pietambaram ,  Suddhasattwa Nad ,  Gang Duan

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L23/49816 ,  H01L23/5381 ,  H01L24/05 ,  H01L24/80 ,  H01L25/0655 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/08225 ,  H01L2224/80444 ,  H01L2224/8049 ,  H01L2924/0105 ,  H01L2924/0132

Abstract: Technologies for die recycling for high yield packaging is disclosed. In the illustrative embodiment, a release layer is deposited on one or more dies. The release layer includes conductive pads and a dielectric layer. Both the conductive pads and the dielectric layer have melting points between a temperature at which the die assembly will be processed and a temperature at which the die may sustain damage. One or more layers such as redistribution layers are deposited on the release layer. If a fault is discovered in the redistribution layers, the die assembly can be heated up past the melting point of the release layer, allowing the die to be removed. The die can then be cleaned and recycled for another packaging attempt.

公开(公告)号：US20240222279A1

公开(公告)日：2024-07-04

申请号：US18091560

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Brandon Christian Marin ,  Srinivas V. Pietambaram ,  Gang Duan ,  Suddhasattwa Nad

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/15 ,  H01L23/42 ,  H01L23/48 ,  H01L25/00 ,  H01L25/16 ,  H01L25/18

CPC classification number: H01L23/5381 ,  H01L21/481 ,  H01L23/15 ,  H01L23/42 ,  H01L23/481 ,  H01L23/5384 ,  H01L24/08 ,  H01L25/167 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145

Abstract: Technologies for a vertically interconnected glass layer architecture is disclosed. In the illustrative embodiment, an integrated circuit component includes several integrated circuit dies and a glass layer. Integrated circuit dies are positioned both above and below the glass layer. The glass layer has a bridge die embedded in a cavity. The bridge die provides interconnects between the various dies and to other components off of the integrated circuit component. The glass layer can enable three-dimensional heterogeneous integration, allowing for fine pitch connections between dies.

公开(公告)号：US20240222219A1

公开(公告)日：2024-07-04

申请号：US18090883

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Gang Duan ,  Srinivas Pietambaram ,  Brandon Marin ,  Suddhasattwa Nad ,  Jeremy Ecton ,  Yang Wu ,  Minglu Liu ,  Yosuke Kanaoka

IPC: H01L23/367 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/42 ,  H01L23/48 ,  H01L23/538 ,  H01L25/18

CPC classification number: H01L23/367 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/42 ,  H01L23/481 ,  H01L23/5381 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253

Abstract: Microelectronic integrated circuit package structures include a first die and a second die both coupled to a bridge structure at an interface. A first thermally conductive mold material is on a first side of the interface and surrounds the first die and the second die. A second mold material is on a second, opposing side of the interface and surrounds the bridge structure.

公开(公告)号：US20240219645A1

公开(公告)日：2024-07-04

申请号：US18090253

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Brandon Marin ,  Jeremy Ecton ,  Gang Duan ,  Srinivas Pietambaram

IPC: G02B6/35

CPC classification number: G02B6/356 ,  G02B6/3596 ,  G02B6/3598

Abstract: An integrated circuit (IC) module includes a photonic IC, an electrical IC, and a switchable waveguide device that, using a signal from the electrical IC, controls optical signals to or from the photonic IC. The switchable waveguide device may be formed by coupling metallization structures on both sides of, and either level with or below, a nonlinear optical material. The metallization structures may be in the photonic or electrical IC. The nonlinear optical material may be above the electrical IC in the photonic IC or on a glass substrate. The photonic and electrical ICs may be hybrid bonded or soldered together. The IC module may be coupled to a system substrate.

公开(公告)号：US20240176085A1

公开(公告)日：2024-05-30

申请号：US18059074

申请日：2022-11-28

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Srinivas V. Pietambaram ,  Gang Duan ,  Suddhasattwa Nad

IPC: G02B6/43 ,  G02B6/122 ,  G02B6/30

CPC classification number: G02B6/43 ,  G02B6/122 ,  G02B6/30

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a photonic assembly may include a substrate having a core with a surface, wherein a material of the core includes glass; and a dielectric material on a portion of the surface of the core, the dielectric material including conductive pathways; a photonic integrated circuit (PIC) electrically coupled to the conductive pathways in the dielectric material; a first optical component between the PIC and the surface of the core, wherein the first optical component is along a perimeter of the core; and a second optical component coupled to the first optical component, wherein the second optical component is optically coupled to the PIC by an optical pathway through the first optical component.

公开(公告)号：US20240170351A1

公开(公告)日：2024-05-23

申请号：US17992010

申请日：2022-11-22

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Gang Duan ,  Brandon Christian Marin ,  Suddhasattwa Nad ,  Srinivas V. Pietambaram

IPC: H01L23/13 ,  H01L21/48 ,  H01L23/00 ,  H01L23/15 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16

CPC classification number: H01L23/13 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L25/167 ,  H01L23/49833 ,  H01L23/5385 ,  H01L2224/1601 ,  H01L2224/16057 ,  H01L2224/1607 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/17055 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/1511 ,  H01L2924/15153 ,  H01L2924/15174 ,  H01L2924/15788

Abstract: Architectures and processes for redistribution layers in a dielectric cavity to enable an embedded component in semiconductor packaging. The architectures pattern redistribution layers (RDL) over a thick seed and remove dielectric material from the RDL conductive contacts to create the dielectric cavity. The architectures enable 2-sided connections for embedded components in the dielectric cavity with minimal disruption to existing process infrastructure. Such an approach can be used not only for integration of photonic devices, but also for any semiconductor packaging requiring dual sided connection within a dielectric cavity.