公开(公告)号：US20250006613A1

公开(公告)日：2025-01-02

申请号：US18883807

申请日：2024-09-12

Applicant: Intel Corporation

Inventor： Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Minglu Liu

IPC: H01L23/498 ,  H01L23/15 ,  H01L23/538 ,  H01L25/065

Abstract: Systems, apparatus, articles of manufacture, and methods for package substrates with stacks of glass layers including interconnect bridges are disclosed. An example substrate for an integrated circuit package includes: a first glass layer having a cavity defined therein; a second glass layer different from the first glass layer; and an interconnect bridge at least partially in the cavity. The interconnect bridge electrically couples a first semiconductor die to a second semiconductor die.

公开(公告)号：US20250006612A1

公开(公告)日：2025-01-02

申请号：US18883796

申请日：2024-09-12

Applicant: Intel Corporation

Inventor： Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Minglu Liu

IPC: H01L23/498 ,  H01L23/15 ,  H01L23/64 ,  H01L25/065

Abstract: Systems, apparatus, articles of manufacture, and methods for power delivery through package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. An example substrate for an integrated circuit package includes: a first glass layer having a first coefficient of thermal expansion (CTE); a second glass layer having a second CTE, the second CTE different from the first CTE; a conductive material extending through a first hole in the first glass layer and a second hole in the second glass layer; and a magnetic material between an inner wall of the first hole and the conductive material.

公开(公告)号：US20250112085A1

公开(公告)日：2025-04-03

申请号：US18375244

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Ziyin Lin ,  Haobo Chen ,  Yiqun Bai ,  Kyle Arrington ,  Jose Waimin ,  Ryan Carrazzone ,  Hongxia Feng ,  Dingying Xu ,  Srinivas Pietambaram ,  Minglu Liu ,  Seyyed Yahya Mousavi ,  Xinyu Li ,  Gang Duan ,  Wei Li ,  Bin Mu ,  Mohit Gupta ,  Jeremy Ecton ,  Brandon C. Marin ,  Xiaoying Guo ,  Ashay Dani

IPC: H01L21/762 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

Abstract: An apparatus is provided which comprises: a plurality of interconnect layers within a substrate, organic dielectric material over the plurality of interconnect layers, copper pads on a surface of a cavity within the organic dielectric material, an integrated circuit bridge device coupled with the copper pads, wherein a surface of the integrated circuit bridge device is elevated above an opening of the cavity, underfill material between the integrated circuit bridge device and the surface of the cavity, and build-up layers formed over the organic dielectric material around the integrated circuit bridge device. Other embodiments are also disclosed and claimed.

公开(公告)号：US20250006609A1

公开(公告)日：2025-01-02

申请号：US18883752

申请日：2024-09-12

Applicant: Intel Corporation

Inventor： Gang Duan ,  Ibrahim El Khatib ,  Jesse Cole Jones ,  Yi Li ,  Minglu Liu ,  Robin Shea McRee ,  Srinivas Venkata Ramanuja Pietambaram ,  Praveen Sreeramagiri

IPC: H01L23/498 ,  H01L23/15 ,  H01L25/065

Abstract: Systems, apparatus, articles of manufacture, and methods for package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. An example package substrate includes: a first glass layer including a first through glass via extending therethrough, the first glass layer having a first coefficient of thermal expansion (CTE); and a second glass layer including a second through glass via extending therethrough, the second glass layer having a second CTE different from the first CTE, the first through glass via electrically coupled to the second through glass via.

公开(公告)号：US20240222219A1

公开(公告)日：2024-07-04

申请号：US18090883

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Gang Duan ,  Srinivas Pietambaram ,  Brandon Marin ,  Suddhasattwa Nad ,  Jeremy Ecton ,  Yang Wu ,  Minglu Liu ,  Yosuke Kanaoka

IPC: H01L23/367 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/42 ,  H01L23/48 ,  H01L23/538 ,  H01L25/18

CPC classification number: H01L23/367 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/42 ,  H01L23/481 ,  H01L23/5381 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253

Abstract: Microelectronic integrated circuit package structures include a first die and a second die both coupled to a bridge structure at an interface. A first thermally conductive mold material is on a first side of the interface and surrounds the first die and the second die. A second mold material is on a second, opposing side of the interface and surrounds the bridge structure.

公开(公告)号：US20250105209A1

公开(公告)日：2025-03-27

申请号：US18475373

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Gang Duan ,  Yosuke Kanaoka ,  Minglu Liu ,  Srinivas V. Pietambaram ,  Brandon C. Marin ,  Bohan Shan ,  Haobo Chen ,  Jeremy Ecton ,  Benjamin T. Duong ,  Suddhasattwa Nad

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/42 ,  H01L23/538 ,  H10B80/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer having first dies in a first insulating material; a second layer on the first layer, the second layer including second dies having a first thickness and third dies having a second thickness different than the first thickness, the second dies and the third dies in a second insulating material, wherein the second dies and third dies have a first surface and an opposing second surface, and wherein the first surfaces of the second and third dies have a combined surface area between 3,000 square millimeters (mm2) and 9,000 mm2; and a redistribution layer (RDL) between the first layer and the second layer, the RDL including conductive pathways, wherein the first dies are electrically coupled to the second dies and the third dies by the conductive pathways and by interconnects.

公开(公告)号：US20250006665A1

公开(公告)日：2025-01-02

申请号：US18883825

申请日：2024-09-12

Applicant: Intel Corporation

Inventor： Gang Duan ,  Minglu Liu ,  Srinivas Venkata Ramanuja Pietambaram

IPC: H01L23/64 ,  H01L23/00 ,  H01L23/15 ,  H01L23/31 ,  H01L23/498 ,  H01L23/535 ,  H01L25/11 ,  H01L25/18 ,  H01L29/66

Abstract: Systems, apparatus, articles of manufacture, and methods for stacks of glass layers including deep trench capacitors are disclosed. An example substrate for an integrated circuit package disclosed herein includes a first glass layer, a second glass layer coupled to the first glass layer, and a deep trench capacitor embedded in the first core.

公开(公告)号：US20250006611A1

公开(公告)日：2025-01-02

申请号：US18883786

申请日：2024-09-12

Applicant: Intel Corporation

Inventor： Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Minglu Liu

IPC: H01L23/498 ,  H01L23/15 ,  H01L23/64 ,  H01L25/065

Abstract: Systems, apparatus, articles of manufacture, and methods for power delivery through package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. An example integrated circuit (IC) package includes: a package core including a first glass sheet and a second glass sheet distinct from the first glass sheet, the first glass sheet having a different coefficient of thermal expansion (CTE) from the second glass sheet; a first redistribution layer on a first side of the package core; a second redistribution layer on a second side of the package core, the second side opposite the first side; and an interconnect extending through the package core, the interconnect including a magnetic material.

公开(公告)号：US20250006610A1

公开(公告)日：2025-01-02

申请号：US18883781

申请日：2024-09-12

Applicant: Intel Corporation

Inventor： Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Minglu Liu

IPC: H01L23/498 ,  H01L23/15 ,  H01L25/065

Abstract: Systems, apparatus, articles of manufacture, and methods for power delivery through package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. An example substrate for an integrated circuit package includes: a first glass layer having a first coefficient of thermal expansion (CTE); a second glass layer having a second CTE, the second CTE different from the first CTE; and a magnetic material lining a first wall of a first opening in the first glass layer and lining a second wall of a second opening in the second glass layer.

公开(公告)号：US20250112162A1

公开(公告)日：2025-04-03

申请号：US18375469

申请日：2023-09-30

Applicant: Intel Corporation

Inventor： Zheng Kang ,  Tchefor Ndukum ,  Yosuke Kanaoka ,  Jeremy Ecton ,  Gang Duan ,  Jefferson Kaplan ,  Yonggang Yong Li ,  Minglu Liu ,  Brandon C. Marin ,  Bai Nie ,  Srinivas Pietambaram ,  Shriya Seshadri ,  Bohan Shan ,  Deniz Turan ,  Vishal Bhimrao Zade

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00

Abstract: An electronic package comprises a substrate core; one or more dielectric material layers over the substrate core and having a lower dielectric material layer, and a plurality of metallization layers comprising an upper-most metallization layer; an integrated circuit (IC) die embedded within the dielectric material and below the upper-most metallization layer; and at least one conductive feature below and coupled to the IC die. A downwardly facing surface of the conductive feature is located on the lower dielectric material layer and defines a horizontal plane at a junction between the conductive feature and the lower dielectric material layer. The lower dielectric material layer has an upper facing surface facing in a direction of the IC die adjacent the conductive feature that is vertically offset from the horizontal plane.