公开(公告)号：US20180233469A1

公开(公告)日：2018-08-16

申请号：US15949632

申请日：2018-04-10

Applicant: Infineon Technologies AG

Inventor： Petteri Palm ,  Thorsten Scharf

IPC: H01L23/00

CPC classification number: H01L24/06 ,  H01L24/19 ,  H01L24/83 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/06182 ,  H01L2224/12105 ,  H01L2224/2518 ,  H01L2224/73267 ,  H01L2224/8019 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2224/83447 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15747

Abstract: A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.

公开(公告)号：US20240332136A1

公开(公告)日：2024-10-03

申请号：US18609133

申请日：2024-03-19

Applicant: Infineon Technologies AG

Inventor： Marco Bäßler ,  Michal Chajneta ,  Thorsten Scharf ,  Egbert Lamminger

IPC: H01L23/495

CPC classification number: H01L23/49537 ,  H01L23/49548 ,  H01L23/49575

Abstract: A power semiconductor device includes: at least one substrate; at least one power semiconductor die arranged over the at least one substrate; a first leadframe arranged over the at least one power semiconductor substrate and over the at least one power semiconductor die, the first leadframe being arranged at least partially in a first plane and including one or more connecting portions extending out of the first plane in a first direction; and a second leadframe at least partially arranged in a second plane above or below the first plane and including one or more attachment sites. The one or more connecting portions extend into the second plane at the one or more attachment sites. The one or more connecting portions are arranged at a non-zero distance from the second leadframe, the non-zero distance being bridged by weld seams at the one or more attachment sites.

公开(公告)号：US20230361088A1

公开(公告)日：2023-11-09

申请号：US18130952

申请日：2023-04-05

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin ,  Thorsten Scharf ,  Marco Bäßler ,  Andreas Grassmann ,  Waldemar Jakobi

IPC: H01L25/07 ,  H01L23/495 ,  H01L23/498

CPC classification number: H01L25/072 ,  H01L23/4952 ,  H01L23/49537 ,  H01L23/49575 ,  H01L23/49811 ,  H01L23/49833 ,  H01L24/48

Abstract: A power semiconductor package includes first power semiconductor dies attached to a metallization layer of at least one first power electronics carrier and second power semiconductor dies attached to a metallization layer of at least one second power electronics carrier. A first lead frame includes a first structured metal frame electrically connected to a load terminal of each first power semiconductor die, and a second structured metal frame electrically connected to a load terminal of each second power semiconductor die and to the metallization layer of the first power electronics carrier. A second lead frame above the first lead frame includes first and second leads electrically connected to the metallization layer of the second power electronics carrier, a third lead between the first and second leads and electrically connected to the first structured metal frame, and a fourth lead electrically connected to the second structured metal frame.

公开(公告)号：US11710684B2

公开(公告)日：2023-07-25

申请号：US17070427

申请日：2020-10-14

Applicant: Infineon Technologies AG

Inventor： Frank Singer ,  Martin Gruber ,  Thorsten Meyer ,  Thorsten Scharf ,  Peter Strobel ,  Stefan Woetzel

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/31 ,  H01L21/54 ,  H01L23/16

CPC classification number: H01L23/49575 ,  H01L21/54 ,  H01L21/56 ,  H01L23/16 ,  H01L23/31 ,  H01L23/49541

Abstract: A package is disclosed. In one example, the package comprises a substrate having at least one first recess on a front side and at least one second recess on a back side, wherein the substrate is separated into a plurality of separate substrate sections by the at least one first recess and the at least one second recess, an electronic component mounted on the front side of the substrate, and a single encapsulant filling at least part of the at least one first recess and at least part of the at least one second recess. The encapsulant fully circumferentially surrounds sidewalls of at least one of the substrate sections.

公开(公告)号：US20230170319A1

公开(公告)日：2023-06-01

申请号：US18103204

申请日：2023-01-30

Applicant: Infineon Technologies AG

Inventor： Petteri Palm ,  Thorsten Scharf

IPC: H01L23/00 ,  H01L23/538 ,  H05K3/00 ,  H05K1/18 ,  H01L25/04

CPC classification number: H01L24/06 ,  H01L24/19 ,  H01L23/5389 ,  H05K3/007 ,  H01L24/20 ,  H05K1/188 ,  H01L25/04 ,  H01L24/83 ,  H01L2924/15747 ,  H01L2924/13055 ,  H01L2224/83192 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2224/12105 ,  H01L2224/83132 ,  H01L2224/73267 ,  H01L2224/04105 ,  H01L2224/83447 ,  H05K2203/0152 ,  H01L2224/06182 ,  H01L2224/8019 ,  H01L2924/00

Abstract: A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.

公开(公告)号：US11469161B2

公开(公告)日：2022-10-11

申请号：US17004070

申请日：2020-08-27

Applicant: Infineon Technologies AG

Inventor： Thorsten Scharf ,  Chan Lam Cha ,  Wolfgang Hetzel ,  Swee Kah Lee ,  Stefan Macheiner

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48

Abstract: A semiconductor package includes: a lead frame having a plurality of blocks of uniform size and laterally spaced apart from one another with uniform spacing; a first semiconductor die attached to a first group of the blocks; electrical conductors connecting a plurality of input/output (I/O) terminals of the first semiconductor die to a second group of the blocks, at least some blocks of the second group being laterally spaced outward from the blocks of the first group; and a mold compound encapsulating the first semiconductor die and the electrical conductors. Corresponding methods of producing the semiconductor package are also described.

公开(公告)号：US20220068773A1

公开(公告)日：2022-03-03

申请号：US17004070

申请日：2020-08-27

Applicant: Infineon Technologies AG

Inventor： Thorsten Scharf ,  Chan Lam Cha ,  Wolfgang Hetzel ,  Swee Kah Lee ,  Stefan Macheiner

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes: a lead frame having a plurality of blocks of uniform size and laterally spaced apart from one another with uniform spacing; a first semiconductor die attached to a first group of the blocks; electrical conductors connecting a plurality of input/output (I/O) terminals of the first semiconductor die to a second group of the blocks, at least some blocks of the second group being laterally spaced outward from the blocks of the first group; and a mold compound encapsulating the first semiconductor die and the electrical conductors. Corresponding methods of producing the semiconductor package are also described.

公开(公告)号：US20210217633A1

公开(公告)日：2021-07-15

申请号：US17217473

申请日：2021-03-30

Applicant: Infineon Technologies AG

Inventor： Richard Knipper ,  Thorsten Scharf

IPC: H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L21/027

Abstract: A semiconductor device includes: a first semiconductor die having opposing first and second main surfaces and an edge between the first and second main surfaces; a molding compound covering the edge and a peripheral part of the first main surface of the first semiconductor die, the molding compound including a resin and filler particles embedded within the resin; and a first opening in the molding compound which exposes a first part of the first main surface of the first semiconductor die from the molding compound, the first part being positioned inward from the peripheral part, wherein the first opening in the molding compound has a sidewall, wherein predominantly all of the filler particles disposed along the sidewall of the first opening are fully embedded within the resin and not exposed at all along the sidewall. A semiconductor structure including a semiconductor wafer or panel is also described.

公开(公告)号：US20210111108A1

公开(公告)日：2021-04-15

申请号：US17070427

申请日：2020-10-14

Applicant: Infineon Technologies AG

Inventor： Frank Singer ,  Martin Gruber ,  Thorsten Meyer ,  Thorsten Scharf ,  Peter Strobel ,  Stefan Woetzel

IPC: H01L23/495 ,  H01L23/16 ,  H01L23/31 ,  H01L21/54 ,  H01L21/56

Abstract: A package is disclosed. In one example, the package comprises a substrate having at least one first recess on a front side and at least one second recess on a back side, wherein the substrate is separated into a plurality of separate substrate sections by the at least one first recess and the at least one second recess, an electronic component mounted on the front side of the substrate, and a single encapsulant filling at least part of the at least one first recess and at least part of the at least one second recess. The encapsulant fully circumferentially surrounds sidewalls of at least one of the substrate sections.

公开(公告)号：US10971457B2

公开(公告)日：2021-04-06

申请号：US16382866

申请日：2019-04-12

Applicant: Infineon Technologies AG

Inventor： Thomas Bemmerl ,  Martin Gruber ,  Thorsten Scharf

IPC: H01L23/00 ,  H01L23/495 ,  H01L21/48

Abstract: A semiconductor device is disclosed. In one example, the semiconductor device comprises a first semiconductor die comprising a first surface, a second surface opposite to the first surface, and a contact pad disposed on the first surface, a further contact pad spaced apart from the semiconductor die, a clip comprising a first layer of a first metallic material and a second layer of a second metallic material different from the first metallic material, wherein the first layer of the clip is connected with the contact pad, and the second layer of the clip is connected with the further contact pad.