公开(公告)号：US20240224543A1

公开(公告)日：2024-07-04

申请号：US18091264

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Gang Duan ,  Srinivas Pietambaram ,  Brandon Marin ,  Jeremy Ecton

IPC: H10B80/00 ,  H01L21/48 ,  H01L23/15 ,  H01L23/498

CPC classification number: H10B80/00 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49827

Abstract: Multi-chip/die device including a logic IC die facing a first side of a glass substrate and a memory IC die facing, and coupled to, the logic IC die. First ones of first metallization features of the logic IC die are coupled to through-glass vias extending through a thickness of the glass substrate. The memory IC die is coupled to second ones of the first metallization features, either directly or by way of other through-glass vias. The logic IC die and/or memory IC die may be directly bonded to the through-glass vias or may be attached by solder. The logic IC die or memory IC die may be embedded within the glass substrate. Through-glass vias within a region beyond an edge of the memory IC die may couple the logic IC die to a host component either through a routing structure built up adjacent the memory IC die, or through solder features attached to the glass substrate adjacent to the memory IC die.

公开(公告)号：US20240222298A1

公开(公告)日：2024-07-04

申请号：US18091583

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Brandon Christian Marin ,  Srinivas V. Pietambaram ,  Suddhasattwa Nad ,  Gang Duan

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L23/49816 ,  H01L23/5381 ,  H01L24/05 ,  H01L24/80 ,  H01L25/0655 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/08225 ,  H01L2224/80444 ,  H01L2224/8049 ,  H01L2924/0105 ,  H01L2924/0132

Abstract: Technologies for die recycling for high yield packaging is disclosed. In the illustrative embodiment, a release layer is deposited on one or more dies. The release layer includes conductive pads and a dielectric layer. Both the conductive pads and the dielectric layer have melting points between a temperature at which the die assembly will be processed and a temperature at which the die may sustain damage. One or more layers such as redistribution layers are deposited on the release layer. If a fault is discovered in the redistribution layers, the die assembly can be heated up past the melting point of the release layer, allowing the die to be removed. The die can then be cleaned and recycled for another packaging attempt.

公开(公告)号：US20240222293A1

公开(公告)日：2024-07-04

申请号：US18091616

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Srinivas V. Pietambaram ,  Gang Duan ,  Siddharth Alur Narasimha Krishna ,  Sameer R. Paital ,  Helme A. Castro De la Torre

IPC: H01L23/58 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/58 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827

Abstract: Technologies for ribbon field-effect transistors with variable fin numbers are disclosed. In an illustrative embodiment, a stack of semiconductor fins is formed, with each semiconductor fin having a source region, a channel region, and a drain region. Some or all of the channel regions can be selectively removed, allowing for the drive and/or leakage current to be tuned. In some embodiments, one or more of the semiconductor fins near the top of the stack can be removed. In other embodiments, one or more of the semiconductor fins at or closer to the bottom of the stack can be removed.

公开(公告)号：US20240222279A1

公开(公告)日：2024-07-04

申请号：US18091560

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Brandon Christian Marin ,  Srinivas V. Pietambaram ,  Gang Duan ,  Suddhasattwa Nad

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/15 ,  H01L23/42 ,  H01L23/48 ,  H01L25/00 ,  H01L25/16 ,  H01L25/18

CPC classification number: H01L23/5381 ,  H01L21/481 ,  H01L23/15 ,  H01L23/42 ,  H01L23/481 ,  H01L23/5384 ,  H01L24/08 ,  H01L25/167 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145

Abstract: Technologies for a vertically interconnected glass layer architecture is disclosed. In the illustrative embodiment, an integrated circuit component includes several integrated circuit dies and a glass layer. Integrated circuit dies are positioned both above and below the glass layer. The glass layer has a bridge die embedded in a cavity. The bridge die provides interconnects between the various dies and to other components off of the integrated circuit component. The glass layer can enable three-dimensional heterogeneous integration, allowing for fine pitch connections between dies.

公开(公告)号：US20240222219A1

公开(公告)日：2024-07-04

申请号：US18090883

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Gang Duan ,  Srinivas Pietambaram ,  Brandon Marin ,  Suddhasattwa Nad ,  Jeremy Ecton ,  Yang Wu ,  Minglu Liu ,  Yosuke Kanaoka

IPC: H01L23/367 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/42 ,  H01L23/48 ,  H01L23/538 ,  H01L25/18

CPC classification number: H01L23/367 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/42 ,  H01L23/481 ,  H01L23/5381 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253

Abstract: Microelectronic integrated circuit package structures include a first die and a second die both coupled to a bridge structure at an interface. A first thermally conductive mold material is on a first side of the interface and surrounds the first die and the second die. A second mold material is on a second, opposing side of the interface and surrounds the bridge structure.

公开(公告)号：US20240219660A1

公开(公告)日：2024-07-04

申请号：US18089934

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Hongxia Feng ,  Haobo Chen ,  Yiqun Bai ,  Dingying Xu ,  Eric J.M. Moret ,  Robert Alan May ,  Srinivas Venkata Ramanuja Pietambaram ,  Tarek A. Ibrahim ,  Gang Duan ,  Xiaoying Guo ,  Ziyin Lin ,  Bai Nie ,  Kyle Jordan Arrington ,  Bin Mu

IPC: G02B6/42 ,  G02B5/10

CPC classification number: G02B6/4246 ,  G02B5/10 ,  G02B6/4274

Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.

公开(公告)号：US20240219655A1

公开(公告)日：2024-07-04

申请号：US18089916

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Haobo Chen ,  Bohan Shan ,  Bai Nie ,  Brandon C. Marin ,  Dingying Xu ,  Gang Duan ,  Hongxia Feng ,  Jeremy D. Ecton ,  Kristof Darmawikarta ,  Kyle Jordan Arrington ,  Srinivas Venkata Ramanuja Pietambaram ,  Xiaoying Guo ,  Yiqun Bai ,  Ziyin Lin

IPC: G02B6/42 ,  H01L21/48

CPC classification number: G02B6/4214 ,  H01L21/4803 ,  H01L23/49827

Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.

公开(公告)号：US20240219645A1

公开(公告)日：2024-07-04

申请号：US18090253

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Brandon Marin ,  Jeremy Ecton ,  Gang Duan ,  Srinivas Pietambaram

IPC: G02B6/35

CPC classification number: G02B6/356 ,  G02B6/3596 ,  G02B6/3598

Abstract: An integrated circuit (IC) module includes a photonic IC, an electrical IC, and a switchable waveguide device that, using a signal from the electrical IC, controls optical signals to or from the photonic IC. The switchable waveguide device may be formed by coupling metallization structures on both sides of, and either level with or below, a nonlinear optical material. The metallization structures may be in the photonic or electrical IC. The nonlinear optical material may be above the electrical IC in the photonic IC or on a glass substrate. The photonic and electrical ICs may be hybrid bonded or soldered together. The IC module may be coupled to a system substrate.

公开(公告)号：US20240186227A1

公开(公告)日：2024-06-06

申请号：US18061181

申请日：2022-12-02

Applicant: Intel Corporation

Inventor： Haobo Chen ,  Bohan Shan ,  Kyle J. Arrington ,  Kristof Darmawikarta ,  Gang Duan ,  Jeremy D. Ecton ,  Hongxia Feng ,  Xiaoying Guo ,  Ziyin Lin ,  Brandon Christian Marin ,  Srinivas V. Pietambaram ,  Dingying Xu

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L23/64 ,  H01L25/065 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K1/18 ,  H05K3/46

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/642 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H05K1/0271 ,  H05K1/0306 ,  H05K1/113 ,  H05K1/181 ,  H05K3/4605 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/157 ,  H01L2924/15788 ,  H05K2201/0195

Abstract: In one embodiment, an integrated circuit package substrate includes a core layer comprising a plurality of metal vias electrically coupling a first side of the core layer and a second side of the core layer opposite the first side. The package substrate further includes a build-up layer on the first side of the core layer, the build-up layer comprising metal vias within a dielectric material and electrically connected to the metal vias of the core layer. The dielectric material includes Silicon, Oxygen, and at least one of Boron or Phosphorus.

公开(公告)号：US20240176085A1

公开(公告)日：2024-05-30

申请号：US18059074

申请日：2022-11-28

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Srinivas V. Pietambaram ,  Gang Duan ,  Suddhasattwa Nad

IPC: G02B6/43 ,  G02B6/122 ,  G02B6/30

CPC classification number: G02B6/43 ,  G02B6/122 ,  G02B6/30

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a photonic assembly may include a substrate having a core with a surface, wherein a material of the core includes glass; and a dielectric material on a portion of the surface of the core, the dielectric material including conductive pathways; a photonic integrated circuit (PIC) electrically coupled to the conductive pathways in the dielectric material; a first optical component between the PIC and the surface of the core, wherein the first optical component is along a perimeter of the core; and a second optical component coupled to the first optical component, wherein the second optical component is optically coupled to the PIC by an optical pathway through the first optical component.