公开(公告)号：US20230197622A1

公开(公告)日：2023-06-22

申请号：US17559431

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Karumbu Meyyappan ,  Jeffory L, Smalley ,  Gregorio Murtagian ,  Srikant Nekkanty ,  Pooya Tadayon ,  Eric J.M. Moret ,  Bijoyraj Sahu

IPC: H01L23/538 ,  H01L23/498 ,  H01R12/52 ,  H01L25/00 ,  H01L25/18 ,  H01L25/065 ,  H01R12/58 ,  H05K3/32 ,  H05K1/18

CPC classification number: H01L23/5384 ,  H01L23/49827 ,  H01L23/5385 ,  H01R12/52 ,  H01L25/50 ,  H01L25/18 ,  H01L25/0655 ,  H01R12/58 ,  H05K3/32 ,  H05K1/181 ,  H05K2201/10189 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/1053

Abstract: An electronic system and associated methods are disclosed. In one example, the electronic system includes an interposer including electrically conductive interposer interconnect, a first interposer surface, and a second interposer surface; a processor package including at least one processor integrated circuit (IC), the processor package attached to the first interposer surface and electrically connected to the interposer interconnect; a first liquid metal well array including multiple liquid metal wells attached to a second interposer surface and the interposer interconnect; a second liquid metal well array including a first array surface attached to the first interposer surface and the interposer interconnect; and a packaged companion IC to the processor IC attached to a second array surface of the second liquid metal well array.

公开(公告)号：US20230197594A1

公开(公告)日：2023-06-22

申请号：US17559483

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Karumbu Meyyappan ,  Jeffory L. Smalley ,  Gregorio Murtagian ,  Srikant Nekkanty ,  Eric J.M. Moret ,  Pooya Tadayon

IPC: H01L23/498 ,  H05K3/32 ,  H05K1/18 ,  H01L23/538 ,  H01R12/52 ,  H01L25/00 ,  H01L25/18 ,  H01L25/065 ,  H01R12/58

CPC classification number: H01L23/49827 ,  H05K3/32 ,  H05K1/181 ,  H01L23/5385 ,  H01R12/52 ,  H01L25/50 ,  H01L25/18 ,  H01L25/0655 ,  H01L23/5384 ,  H01R12/58 ,  H05K2201/10189 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/1053

Abstract: An electronic system and associated methods are disclosed. In one example, the electronic system includes a processor package including at least one processor integrated circuit (IC); an interposer including electrically conductive interposer interconnect; a first liquid metal well array including multiple liquid metal wells arranged between the processor package and the interposer, wherein the first liquid metal well array is attached to a surface of the processor package and attached to a first surface of the interposer and the interposer interconnect; a printed circuit board (PCB) attached to a second surface of the interposer and the interposer interconnect; a second liquid metal well array including a first surface attached to the first surface of the interposer and the interposer interconnect; and a first companion component package attached to a second surface of the second liquid metal well array.

公开(公告)号：US20180067160A1

公开(公告)日：2018-03-08

申请号：US15259934

申请日：2016-09-08

Applicant: Intel Corporation

Inventor： Eric J.M. Moret

IPC: G01R31/28 ,  G01R1/073

CPC classification number: G01R31/2875 ,  G01R1/07392 ,  G01R31/2874 ,  G01R31/2891

Abstract: Embodiments of the present disclosure describe wafer-level die testing devices having a base with a planar X-Y surface, a plurality of thermal actuators situated on the surface, wherein one or more of the plurality of thermal actuators is movable in relation to the base in at least one of the X or the Y directions, and one or more adjustable links, wherein each adjustable link is to adjust a relative position between an individual thermal actuator of the plurality of thermal actuators and one or more other thermal actuators of the plurality of thermal actuators in one or more of the X or the Y directions. Other embodiments may be described and/or claimed.

公开(公告)号：US20230092060A1

公开(公告)日：2023-03-23

申请号：US17479334

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Eric J.M. Moret ,  Srinivas Venkata Ramanuja Pietambaram ,  Tarek A. Ibrahim

IPC: G02B6/42

Abstract: In an optical circuit, a substrate can define a cavity that extends into a substrate front surface. A sidewall of the cavity can include a substrate optical port. An optical path can extend through the substrate from a connector optical port to the substrate optical port. A photonic integrated circuit (PIC) can attach to the substrate. A PIC front surface can include a plurality of electrical connections. A PIC edge surface can extend around at least a portion of a perimeter of the PIC between the PIC front surface and a PIC back surface. A PIC optical port can be disposed on the PIC edge surface and can accept or emit an optical beam along a PIC optical axis. The PIC optical axis can be aligned with the substrate optical port when the PIC is attached to the substrate.

公开(公告)号：US20230087567A1

公开(公告)日：2023-03-23

申请号：US17480420

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Eric J.M. Moret ,  Pooya Tadayon

IPC: G02B6/30

Abstract: In an optical circuit, a substrate can have a substrate top surface, a substrate bottom surface, and a substrate edge surface that extends around at least a portion of a perimeter of the substrate. A photonic integrated circuit (PIC) can be attached to the substrate. The PIC can have a PIC optical port that is configured to accept or emit an optical beam along a PIC optical axis. A lens can be located at the substrate edge surface. The substrate can include an optical path that extends through the substrate from a first substrate optical port that is aligned with the PIC optical axis to a second substrate optical port that faces the lens, such that an optical beam emergent from the PIC optical port can traverse the optical path and pass through the lens to emerge substantially parallel to the substrate top surface.

公开(公告)号：US20240219660A1

公开(公告)日：2024-07-04

申请号：US18089934

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Hongxia Feng ,  Haobo Chen ,  Yiqun Bai ,  Dingying Xu ,  Eric J.M. Moret ,  Robert Alan May ,  Srinivas Venkata Ramanuja Pietambaram ,  Tarek A. Ibrahim ,  Gang Duan ,  Xiaoying Guo ,  Ziyin Lin ,  Bai Nie ,  Kyle Jordan Arrington ,  Bin Mu

IPC: G02B6/42 ,  G02B5/10

CPC classification number: G02B6/4246 ,  G02B5/10 ,  G02B6/4274

Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.

公开(公告)号：US20230197621A1

公开(公告)日：2023-06-22

申请号：US17559365

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Karumbu Meyyappan ,  Jeffory L. Smalley ,  Gregorio Murtagian ,  Srikant Nekkanty ,  Eric J.M. Moret ,  Pooya Tadayon

IPC: H01L23/538 ,  H01L23/498 ,  H01R12/52 ,  H01L25/00 ,  H01L25/18 ,  H01L25/065 ,  H01R12/58

CPC classification number: H01L23/5384 ,  H01L23/49827 ,  H01L23/5385 ,  H01R12/52 ,  H01L25/50 ,  H01L25/18 ,  H01L25/0655 ,  H01R12/58

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes an integrated circuit (IC) package substrate including package interconnect and a first substrate surface; a processor IC attached to the first substrate surface and electrically connected to the package interconnect; a liquid metal well array including multiple liquid metal wells, a first array surface attached to the first substrate surface, and a second array surface; and a companion component to the processor IC attached to the second array surface of the liquid metal well array.

公开(公告)号：US20230101997A1

公开(公告)日：2023-03-30

申请号：US17490290

申请日：2021-09-30

Applicant: Intel Corporation

Inventor： Nikos Kaburlasos ,  Rodrigo De Oliveira Vivi ,  Phani Kumar Kandula ,  Marc Beuchat ,  Mark J. Luckeroth ,  Eric J.M. Moret ,  David N. Lombard ,  John Kelbert ,  Brad Bittel

IPC: G06F1/3296 ,  G06F1/3228 ,  G06F1/08

Abstract: Disclosed herein are embodiments of systems and methods for stable and elevated idle-mode temperature for assembled semiconductor devices. In an embodiment, a processor includes a communication interface configured to receive, from a first hardware component, instructions assigned to the processor for execution. The processor also includes temperature-measurement circuitry configured to monitor an on-chip temperature of the processor. The processor also includes control logic configured to: determine whether the processor is active or idle; determine whether the on-chip temperature of the processor exceeds a first threshold; based on determining that the processor is idle and that the on-chip temperature of the processor exceeds the first threshold, disable one or more idle-mode power-saving features of the processor; and selectively adjust one or more operating parameters of the processor to keep the on-chip temperature of the processor between the first threshold and a second (higher) threshold.