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公开(公告)号：US20230063678A1
公开(公告)日：2023-03-02
申请号：US17465419
申请日：2021-09-02
Applicant: Intel Corporation
Inventor： Scott Janus , Deepak Vembar
Abstract: Methods, systems and apparatuses may provide for technology that detects virtual background content and real-time foreground content associated with a video session, wherein the real-time foreground content depicts a plurality of participants from different physical environments. The technology may also apply a visual correction to one or more of the real-time foreground content or the virtual background content, wherein the visual correction reduces a difference between the real-time foreground content and the virtual background content with respect to one or more lighting parameters and two or more of the plurality of participants. Additionally, the technology may generate a composite result based on the real-time foreground content, the virtual background content, and the visual correction.
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公开(公告)号：US11409658B2
公开(公告)日：2022-08-09
申请号：US17161465
申请日：2021-01-28
Applicant: Intel Corporation
Inventor： Vikranth Vemulapalli , Lakshminarayanan Striramassarma , Mike MacPherson , Aravindh Anantaraman , Ben Ashbaugh , Murali Ramadoss , William B. Sadler , Jonathan Pearce , Scott Janus , Brent Insko , Vasanth Ranganathan , Kamal Sinha , Arthur Hunter, Jr. , Prasoonkumar Surti , Nicolas Galoppo von Borries , Joydeep Ray , Abhishek R. Appu , ElMoustapha Ould-Ahmed-Vall , Altug Koker , Sungye Kim , Subramaniam Maiyuran , Valentin Andrei
IPC: G09G5/36 , G06F12/0862 , G06T1/20 , G06T1/60
Abstract: Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the L1 cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.
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公开(公告)号：US11263799B2
公开(公告)日：2022-03-01
申请号：US16910434
申请日：2020-06-24
Applicant: INTEL CORPORATION
Inventor： Prasoonkumar Surti , Carsten Benthin , Karthik Vaidyanathan , Philip Laws , Scott Janus , Sven Woop
Abstract: Cluster of acceleration engines to accelerate intersections. For example, one embodiment of an apparatus comprises: a set of graphics cores to execute a first set of instructions of a primary graphics thread; a scalar cluster comprising a plurality of scalar execution engines; and a communication fabric interconnecting the set of graphics cores and the scalar cluster; the set of graphics cores to offload execution of a second set of instructions associated with ray traversal and/or intersection operations to the scalar cluster; the scalar cluster comprising a plurality of local memories, each local memory associated with one of the scalar execution engines, wherein each local memory is to store a portion of a hierarchical acceleration data structure required by an associated scalar execution engine to execute one or more of the second set of instructions; the plurality of scalar execution engines to store results of the execution of the second set of instructions in a memory accessible by the set of graphics cores; wherein the set of graphics cores are to process the results within the primary graphics thread.
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44.发明申请公开(公告)号：US20210149763A1
公开(公告)日：2021-05-20
申请号：US17095530
申请日：2020-11-11
Applicant: Intel Corporation
Inventor： Vasanth Ranganathan , Joydeep Ray , Abhishek R. Appu , Nikos Kaburlasos , Lidong Xu , Subramaniam Maiyuran , Altug Koker , Naveen Matam , James Holland , Brent Insko , Sanjeev Jahagirdar , Scott Janus , Durgaprasad Bilagi , Xinmin Tian
IPC: G06F11/10 , G06F12/0802 , G06T1/20 , G06T1/60
Abstract: Apparatuses including a graphics processing unit, graphics multiprocessor, or graphics processor having an error detection correction logic for cache memory or shared memory are disclosed. In one embodiment, a graphics multiprocessor includes cache or local memory for storing data and error detection correction circuitry integrated with or coupled to the cache or local memory. The error detection correction circuitry is configured to perform a tag read for data of the cache or local memory to check error detection correction information.
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公开(公告)号：US10930051B2
公开(公告)日：2021-02-23
申请号：US16235744
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： Scott Janus , Prasoonkumar Surti , Karthik Vaidyanathan , Gabor Liktor , Carsten Benthin , Philip Laws
Abstract: Apparatus and method for general ray tracing queries. For example, one embodiment of an apparatus comprises: a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes associated with a graphics scene; traversal/intersection hardware logic to traverse one or more rays through the acceleration data structure to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; shape processing hardware logic to specify three dimensional (3D) shape data indicating one or more 3D shapes to be used to perform queries with respect to the hierarchical acceleration data structure; query processing hardware logic to execute queries comprising comparisons between nodes of the hierarchical acceleration data structure and the 3D shape data to generate a result indicating overlap between the 3D shapes and the nodes.
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Patent Agency Ranking
公开(公告)号：US10909039B2
公开(公告)日：2021-02-02
申请号：US16355015
申请日：2019-03-15
Applicant: Intel Corporation
Inventor： Vikranth Vemulapalli , Lakshminarayanan Striramassarma , Mike MacPherson , Aravindh Anantaraman , Ben Ashbaugh , Murali Ramadoss , William B. Sadler , Jonathan Pearce , Scott Janus , Brent Insko , Vasanth Ranganathan , Kamal Sinha , Arthur Hunter, Jr. , Prasoonkumar Surti , Nicolas Galoppo von Borries , Joydeep Ray , Abhishek R. Appu , ElMoustapha Ould-Ahmed-Vall , Altug Koker , Sungye Kim , Subramaniam Maiyuran , Valentin Andrei
IPC: G09G5/36 , G06F12/0862 , G06T1/20 , G06T1/60
Abstract: Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the L1 cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.
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公开(公告)号：US20210012722A1
公开(公告)日：2021-01-14
申请号：US16939916
申请日：2020-07-27
Applicant: Intel Corporation
Inventor： Arthur J. Runyan , Richmond Hicks , Nausheen Ansari , Narayan Biswal , Ya-Ti Peng , Abhishek R. Appu , Wen-Fu Kao , Sang-Hee Lee , Joydeep Ray , Changliang Wang , Satyanarayana Avadhanam , Scott Janus , Gary Smith , Nilesh V. Shah , Keith W. Rowe , Robert J. Johnston
IPC: G09G3/34 , G09G3/36 , B60R1/00 , G09G5/10 , G09G5/14 , G09G5/38 , G06F3/147 , G02B27/01 , G09G5/00
Abstract: Often when there is a glare on a display screen the user may be able to mitigate the glare by tilting or otherwise moving the screen or changing their viewing position. However, when driving a car there are limited options for overcoming glares on the dashboard, especially when you are driving for a long distance in the same direction. Embodiments are directed to eliminating such glare. Other embodiments are related to mixed reality (MR) and filling in occluded areas.
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公开(公告)号：US10893299B2
公开(公告)日：2021-01-12
申请号：US16050391
申请日：2018-07-31
Applicant: Intel Corporation
Inventor： Jill Boyce , Scott Janus , Itay Kaufman , Archie Sharma , Stanley Baran , Michael Apodaca , Prasoonkumar Surti , Srikanth Potluri , Barnan Das , Hugues Labbe , Jong Dae Oh , Gokcen Cilingir , Maria Bortman , Tzach Ashkenazi , Jonathan Distler , Atul Divekar , Mayuresh M. Varerkar , Narayan Biswal , Nilesh V. Shah , Atsuo Kuwahara , Kai Xiao , Jason Tanner , Jeffrey Tripp
Abstract: An apparatus to facilitate processing video bit stream data is disclosed. The apparatus includes one or more processors to encode surface normals data with point cloud geometry data included in the video bit stream data for reconstruction of objects within the video bit stream data based on the surface normals data and a memory communicatively coupled to the one or more processors.
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公开(公告)号：US10861225B2
公开(公告)日：2020-12-08
申请号：US16234463
申请日：2018-12-27
Applicant: Intel Corporation
Inventor： Jill Boyce , Soethiha Soe , Selvakumar Panneer , Adam Lake , Nilesh Jain , Deepak Vembar , Glen J. Anderson , Varghese George , Carl Marshall , Scott Janus , Saurabh Tangri , Karthik Veeramani , Prasoonkumar Surti
Abstract: Embodiments are directed to neural network processing for multi-object three-dimensional (3D) modeling. An embodiment of a computer-readable storage medium includes executable computer program instructions for obtaining data from multiple cameras, the data including multiple images, and generating a 3D model for 3D imaging based at least in part on the data from the cameras, wherein generating the 3D model includes one or more of performing processing with a first neural network to determine temporal direction based at least in part on motion of one or more objects identified in an image of the multiple images or performing processing with a second neural network to determine semantic content information for an image of the multiple images.
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公开(公告)号：US20200293450A1
公开(公告)日：2020-09-17
申请号：US16355015
申请日：2019-03-15
Applicant: Intel Corporation
Inventor： Vikranth Vemulapalli , Lakshminarayanan Striramassarma , Mike MacPherson , Aravindh Anantaraman , Ben Ashbaugh , Murali Ramadoss , William B. Sadler , Jonathan Pearce , Scott Janus , Brent Insko , Vasanth Ranganathan , Kamal Sinha , Arthur Hunter, JR. , Prasoonkumar Surti , Nicolas Galoppo von Borries , Joydeep Ray , Abhishek R. Appu , ElMoustapha Ould-Ahmed-Vall , Altug Koker , Sungye Kim , Subramaniam Maiyuran , Valentin Andrei
IPC: G06F12/0862 , G06T1/60 , G06T1/20
Abstract: Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the L1 cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.
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