公开(公告)号：US20190072732A1

公开(公告)日：2019-03-07

申请号：US16182450

申请日：2018-11-06

Applicant: Intel IP Corporation

Inventor： Georg Seidemann ,  Christian Geissler ,  Sven Albers ,  Thomas Wagner ,  Marc Dittes ,  Klaus Reingruber ,  Andreas Wolter ,  Richard Patten

IPC: G02B6/42 ,  G02B6/30 ,  G02B6/122 ,  G02B6/132 ,  G02B6/12

CPC classification number: G02B6/428 ,  G02B6/12002 ,  G02B6/122 ,  G02B6/1221 ,  G02B6/132 ,  G02B6/30 ,  G02B6/4232 ,  G02B6/4238 ,  G02B6/43 ,  G02B2006/12197

Abstract: Disclosed is a package comprising a substrate having a patterned surface with an optical contact area, an optical redistribution layer (oRDL) feature, and a build-up material extending over the patterned surface of the substrate and around portions of the oRDL features. In some embodiments, the package comprises a liner sheathing the oRDL features. In some embodiments, the oRDL feature extends through openings in an outer surface of the build-up material and forms posts extending outward from the outer surface. In some embodiments, the package comprises an electrical redistribution layer (eRDL) feature, at least some portion of which overlap at least some portion of the oRDL feature. In some embodiments, the package comprises an optical fiber coupled to the oRDL features.

公开(公告)号：US10209466B2

公开(公告)日：2019-02-19

申请号：US15089524

申请日：2016-04-02

Applicant: Intel IP Corporation

Inventor： Georg Seidemann ,  Christian Geissler ,  Sven Albers ,  Thomas Wagner ,  Marc Dittes ,  Klaus Reingruber ,  Andreas Wolter ,  Richard Patten

IPC: G02B6/30 ,  G02B6/42 ,  G02B6/122 ,  G02B6/132 ,  G02B6/12

Abstract: Disclosed is a package comprising a substrate having a patterned surface with an optical contact area, an optical redistribution layer (oRDL) feature, and a build-up material extending over the patterned surface of the substrate and around portions of the oRDL features. In some embodiments, the package comprises a liner sheathing the oRDL features. In some embodiments, the oRDL feature extends through openings in an outer surface of the build-up material and forms posts extending outward from the outer surface. In some embodiments, the package comprises an electrical redistribution layer (eRDL) feature, at least some portion of which overlap at least some portion of the oRDL feature. In some embodiments, the package comprises an optical fiber coupled to the oRDL features.

公开(公告)号：US10141265B2

公开(公告)日：2018-11-27

申请号：US15394388

申请日：2016-12-29

Applicant: Intel IP Corporation

Inventor： Bernd Waidhas ,  Stephan Stoeckl ,  Andreas Wolter ,  Reinhard Mahnkopf ,  Georg Seidemann ,  Thomas Wagner ,  Laurent Millou

IPC: H01L23/06 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L23/053

Abstract: A bent-bridge semiconductive apparatus includes a silicon bridge that is integral to a semiconductive device and the silicon bridge is deflected out of planarity. The silicon bridge may couple two semiconductive devices, all of which are from an integral processed die.

公开(公告)号：US20180226185A1

公开(公告)日：2018-08-09

申请号：US15862196

申请日：2018-01-04

Applicant: Intel IP Corporation

Inventor： Sven Albers ,  Klaus Reingruber ,  Andreas Wolter

IPC: H01F27/28 ,  H01F27/24

CPC classification number: H01F27/2804 ,  H01F27/06 ,  H01F27/24 ,  H01F2027/065 ,  H01F2027/2809

Abstract: An electronic package that includes a substrate; a first electronic component mounted on one side of the substrate; a second electronic component mounted on an opposing side of the substrate; a core mounted to the substrate, wherein the core extends through the substrate; a first wire electrically attached to at least one of the first electronic component and the substrate, wherein the first wire is wrapped around the core to form a first coil on the one side of the substrate; and a second wire electrically attached to at least one of the second electronic component and the substrate, wherein the second wire is wrapped around the core to form a second coil on the opposing side of the substrate.

公开(公告)号：US20170285280A1

公开(公告)日：2017-10-05

申请号：US15089524

申请日：2016-04-02

Applicant: Intel IP Corporation

Inventor： Georg Seidemann ,  Christian Geissler ,  Sven Albers ,  Thomas Wagner ,  Marc Dittes ,  Klaus Reingruber ,  Andreas Wolter ,  Richard Patten

IPC: G02B6/42 ,  G02B6/30 ,  G02B6/132 ,  G02B6/122

CPC classification number: G02B6/428 ,  G02B6/12002 ,  G02B6/122 ,  G02B6/1221 ,  G02B6/132 ,  G02B6/30 ,  G02B6/4232 ,  G02B6/4238 ,  G02B6/43 ,  G02B2006/12197

Abstract: Disclosed is a package comprising a substrate having a patterned surface with an optical contact area, an optical redistribution layer (oRDL) feature, and a build-up material extending over the patterned surface of the substrate and around portions of the oRDL features. In some embodiments, the package comprises a liner sheathing the oRDL features. In some embodiments, the oRDL feature extends through openings in an outer surface of the build-up material and forms posts extending outward from the outer surface. In some embodiments, the package comprises an electrical redistribution layer (eRDL) feature, at least some portion of which overlap at least some portion of the oRDL feature. In some embodiments, the package comprises an optical fiber coupled to the oRDL features.

公开(公告)号：US08779564B1

公开(公告)日：2014-07-15

申请号：US13803143

申请日：2013-03-14

Applicant: Intel IP Corporation

Inventor： Mikael Knudsen ,  Thorsten Meyer ,  Saravana Maruthamuthu ,  Andreas Wolter ,  Georg Seidemann ,  Pablo Herrero ,  Pauli Jaervinen

IPC: H01L23/552 ,  H01L27/06

CPC classification number: H01L23/552 ,  H01L23/295 ,  H01L23/48 ,  H01L23/66 ,  H01L24/19 ,  H01L25/0655 ,  H01L2223/6677 ,  H01L2223/6688 ,  H01L2224/12105 ,  H01L2224/73267 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01Q1/2283 ,  H01Q9/0414 ,  H01Q9/0421 ,  H01Q23/00 ,  H01L2924/00

Abstract: A semiconductor device may include: a chip; a chip packaging structure at least partially surrounding the chip and having a receiving region configured to receive a first capacitive coupling structure; a first capacitive coupling structure disposed in the receiving region; and a second capacitive coupling structure disposed over the first capacitive coupling structure and capacitively coupled to the first capacitive coupling structure.

Abstract translation: 半导体器件可以包括：芯片; 芯片封装结构至少部分地围绕芯片并且具有被配置为接收第一电容耦合结构的接收区域; 设置在所述接收区域中的第一电容耦合结构; 以及设置在所述第一电容耦合结构上并且电容耦合到所述第一电容耦合结构的第二电容耦合结构。