公开(公告)号：US20250142909A1

公开(公告)日：2025-05-01

申请号：US19008075

申请日：2025-01-02

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Masihhur R. Laskar ,  Nicholas R. Tapias ,  Darwin Franseda Fan ,  Manuj Nahar

IPC: H10D62/40 ,  H10B12/00 ,  H10B53/30 ,  H10D62/17

Abstract: Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.

公开(公告)号：US12224310B2

公开(公告)日：2025-02-11

申请号：US18531525

申请日：2023-12-06

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Masihhur R. Laskar ,  Nicholas R. Tapias ,  Darwin Franseda Fan ,  Manuj Nahar

IPC: H01L29/10 ,  H01L29/04 ,  H10B12/00 ,  H10B53/30

Abstract: Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.

公开(公告)号：US20240268091A1

公开(公告)日：2024-08-08

申请号：US18432870

申请日：2024-02-05

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Pankaj Sharma ,  Manuj Nahar ,  Nicholas R. Tapias ,  Scott E. Sills

IPC: H10B12/00

CPC classification number: H10B12/00

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first conductive region; a second conductive region; a memory cell between the first and second conductive regions and including a first transistor including a first region coupled to the first and second conductive regions, and a charge storage structure separated from the first conduction region, and a second transistor including a second region coupled to the charge storage structure and the second conductive region; and a structure separated from the first region, the charge storage structure, and the second region by a dielectric structure, the structure forming part of a gate of the first transistor and the second transistor, and the structure including a first portion adjacent the dielectric structure, and a second portion adjacent the first portion, wherein the first portion includes a semiconductor material and the second portion includes a conductive material.

公开(公告)号：US20240164114A1

公开(公告)日：2024-05-16

申请号：US18522637

申请日：2023-11-29

Applicant: Micron Technology, Inc.

Inventor： Hung-Wei Liu ,  Vassil N. Antonov ,  Ashonita A. Chavan ,  Darwin Franseda Fan ,  Jeffery B. Hull ,  Anish A. Khandekar ,  Masihhur R. Laskar ,  Albert Liao ,  Xue-Feng Lin ,  Manuj Nahar ,  Irina V. Vasilyeva

IPC: H10B53/20 ,  H01L21/223 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H10B51/20 ,  H10B51/30 ,  H10B53/30

CPC classification number: H10B53/20 ,  H01L21/223 ,  H01L29/1037 ,  H01L29/66666 ,  H01L29/7827 ,  H10B51/20 ,  H10B51/30 ,  H10B53/30

Abstract: A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.

公开(公告)号：US11862668B2

公开(公告)日：2024-01-02

申请号：US17366557

申请日：2021-07-02

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Masihhur R. Laskar ,  Nicholas R. Tapias ,  Darwin Franseda Fan ,  Manuj Nahar

IPC: H01L29/04 ,  H01L29/10 ,  H10B12/00 ,  H10B53/30

CPC classification number: H01L29/04 ,  H01L29/1033 ,  H10B12/00 ,  H10B53/30

Abstract: Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.

公开(公告)号：US11856790B2

公开(公告)日：2023-12-26

申请号：US18072546

申请日：2022-11-30

Applicant: Micron Technology, Inc.

Inventor： Ashonita A. Chavan ,  Durai Vishak Nirmal Ramaswamy ,  Manuj Nahar

IPC: H01L29/78 ,  H10B53/30 ,  H01L21/28 ,  H10B51/30 ,  H01L21/02 ,  H01L49/02 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H10B53/30 ,  H01L21/02164 ,  H01L21/28088 ,  H01L21/28097 ,  H01L28/55 ,  H01L28/60 ,  H01L29/40111 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/516 ,  H01L29/517 ,  H01L29/6684 ,  H01L29/78391 ,  H10B51/30

Abstract: A method used in forming an electronic component comprising conductive material and ferroelectric material comprises forming a non-ferroelectric metal oxide-comprising insulator material over a substrate. A composite stack comprising at least two different composition non-ferroelectric metal oxides is formed over the substrate. The composite stack has an overall conductivity of at least 1×102 Siemens/cm. The composite stack is used to render the non-ferroelectric metal oxide-comprising insulator material to be ferroelectric. Conductive material is formed over the composite stack and the insulator material. Ferroelectric capacitors and ferroelectric field effect transistors independent of method of manufacture are also disclosed.

公开(公告)号：US11676768B2

公开(公告)日：2023-06-13

申请号：US17865242

申请日：2022-07-14

Applicant: Micron Technology, Inc.

Inventor： Ashonita A. Chavan ,  Beth R. Cook ,  Manuj Nahar ,  Durai Vishak Nirmal Ramaswamy

IPC: G11C11/22 ,  H01L27/115 ,  H01L23/522 ,  H01L23/485 ,  H01L27/06 ,  H01G4/38 ,  H01L27/11507 ,  H01L49/02

CPC classification number: H01G4/385 ,  G11C11/221 ,  H01L27/11507 ,  H01L28/56 ,  H01L28/91

Abstract: Some embodiments include an apparatus having horizontally-spaced bottom electrodes supported by a supporting structure. Leaker device material is directly against the bottom electrodes. Insulative material is over the bottom electrodes, and upper electrodes are over the insulative material. Plate material extends across the upper electrodes and couples the upper electrodes to one another. The plate material is directly against the leaker device material. The leaker device material electrically couples the bottom electrodes to the plate material, and may be configured to discharge at least a portion of excess charge from the bottom electrodes to the plate material. Some embodiments include methods of forming apparatuses which include capacitors having bottom electrodes and top electrodes, with the top electrodes being electrically coupled to one another through a conductive plate. Leaker devices are formed to electrically couple the bottom electrodes to the conductive plate.

公开(公告)号：US20230015304A1

公开(公告)日：2023-01-19

申请号：US17950023

申请日：2022-09-21

Applicant: Micron Technology, Inc.

Inventor： Manuj Nahar ,  Ashonita A. Chavan

IPC: H01G4/10 ,  H01L49/02 ,  H01G4/30 ,  H01L27/1159 ,  H01L29/51 ,  H01L27/11507 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01G4/33 ,  H01G4/40

Abstract: A method used in forming an electronic device comprising conductive material and ferroelectric material comprises forming a composite stack comprising multiple metal oxide-comprising insulator materials. At least one of the metal oxide-comprising insulator materials is between and directly against non-ferroelectric insulating materials. The multiple metal oxide-comprising insulator materials are of different composition from that of immediately-adjacent of the non-ferroelectric insulating materials. The composite stack is subjected to a temperature of at least 200° C. After the subjecting, the composite stack comprises multiple ferroelectric metal oxide-comprising insulator materials at least one of which is between and directly against non-ferroelectric insulating materials. After the subjecting, the composite stack is ferroelectric. Conductive material is formed and that is adjacent the composite stack. Devices are also disclosed.

公开(公告)号：US11532699B2

公开(公告)日：2022-12-20

申请号：US16898029

申请日：2020-06-10

Applicant: Micron Technology, Inc.

Inventor： Michael Mutch ,  Manuj Nahar ,  Wayne I. Kinney

IPC: H01L29/04 ,  H01L21/02 ,  H01L29/161 ,  H01L21/324 ,  H01L29/786 ,  H01L27/105

Abstract: A method includes forming a semiconductor structure. The structure includes a first material, a blocking material, a second material in an amorphous form, and a third material in an amorphous form. The blocking material is disposed between the first material and the second material. At least the second material and the third material each comprise silicon and/or germanium. The structure is exposed to a temperature above a crystallization temperature of the third material and below a crystallization temperature of the second material. Semiconductor structures, memory devices, and systems are also disclosed.

公开(公告)号：US20210175357A1

公开(公告)日：2021-06-10

申请号：US17159594

申请日：2021-01-27

Applicant: Micron Technology, Inc.

Inventor： Manuj Nahar ,  Michael Mutch

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/36 ,  H01L21/02 ,  H01L29/04 ,  H01L29/08 ,  H01L29/66 ,  H01L29/10

Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, and a channel region vertically between the top and bottom source/drain regions. A gate is operatively laterally-adjacent the channel region. The top source/drain region, the bottom source/drain region, and the channel region respectively have crystal grains and grain boundaries between immediately-adjacent of the crystal grains. At least one of the bottom source/drain region and the channel region has an internal interface there-within between the crystal grains that are above the internal interface and the crystal grains that are below the internal interface. At least some of the crystal grains that are immediately-above the internal interface physically contact at least some of the crystal grains that are immediately-below the internal interface. All of the grain boundaries that are between immediately-adjacent of the physically-contacting crystal grains that are immediately-above and that are immediately-below the interface align relative one another. The internal interface comprises at least one of (a) and (b), where (a): conductivity-modifying dopant concentration immediately-above the internal interface is lower than immediately-below the internal interface and (b): a laterally-discontinuous insulative oxide. Other embodiments, including method, are disclosed.