公开(公告)号：US11663121B2

公开(公告)日：2023-05-30

申请号：US17531743

申请日：2021-11-20

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Chi She Chen ,  Jeffery C. Solomon ,  Mario Jesus Martinez ,  Hao Le ,  Soon J. Choi

IPC: G06F12/02 ,  G06F12/08 ,  G06F12/0871 ,  G06F3/06 ,  G11C7/10 ,  G06F13/28 ,  G06F13/10 ,  G06F12/06 ,  G06F12/0897

CPC classification number: G06F12/0246 ,  G06F3/061 ,  G06F3/068 ,  G06F3/0685 ,  G06F12/0638 ,  G06F12/08 ,  G06F12/0871 ,  G06F13/10 ,  G06F13/28 ,  G11C7/1072 ,  G06F3/0656 ,  G06F3/0688 ,  G06F12/0897 ,  G06F2206/1014 ,  G06F2212/205 ,  G06F2212/214 ,  G06F2212/313 ,  G06F2212/7201 ,  G06F2212/7208

Abstract: A memory module comprises a volatile memory subsystem including DRAM, a non-volatile memory subsystem including Flash memory, and a module control device. The Flash memory includes main Flash providing a main Flash memory space and scratch Flash providing a scratch Flash memory space. The module control device is configured to receive a request from the memory controller to move one or more segments of data in a first Flash block in the main Flash to the DRAM and to, for each respective segment of data: select a respective set of pages in the DRAM; transfer respective data stored in the respective set of pages from the DRAM to a corresponding segment in the scratch Flash; and transfer the respective segment of data to the respective set of pages in the DRAM. Thus, data can be moved segment by segment between the DRAM and the Flash memory.

公开(公告)号：US11093417B2

公开(公告)日：2021-08-17

申请号：US16695020

申请日：2019-11-25

Applicant: Netlist, Inc.

Inventor： Jefferey C. Solomon ,  Jayesh R. Bhakta

IPC: G06F12/00 ,  G06F13/16 ,  G11C5/04 ,  G06F13/00 ,  G06F13/42 ,  G11C7/10 ,  G11C15/00

Abstract: A memory module operable to communicate data with a memory controller via a N-bit wide memory bus comprises memory devices arranged in a plurality of N-bit wide ranks. The memory module further comprises logic configurable to receive a set of input address and control signals associated with a read or write memory command and output registered address and control signals and data buffer control signals. The memory module further comprises circuitry coupled between the memory bus and corresponding data pins of memory devices in each of the plurality of N-bit wide ranks. The circuitry is configurable to enable registered transfers of N-bit wide data signals associated with the memory read or write command between the N-bit wide memory bus and the memory devices in response to the data buffer control signals and in accordance with an overall CAS latency of the memory module, which is greater than an actual operational CAS latency of the memory devices.

公开(公告)号：US20190354480A1

公开(公告)日：2019-11-21

申请号：US16432700

申请日：2019-06-05

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G06F12/0802 ,  G11C29/02 ,  G11C7/10 ,  G11C5/04

Abstract: A memory module is operable in a memory system with a memory controller. The memory module comprises a module control device to receive command signals from the memory controller and to output module C/A signals and data buffer control signals. The module C/A signals are provided to memory devices organized in groups, each group including at least one memory device, while the data buffer control signals are provided to a plurality of buffer circuits to control data paths in the buffer circuits, a respective buffer circuit corresponding to a respective group of memory devices. The plurality of buffer circuits are distributed across a surface of the memory module such that each data buffer control signal arrives at the plurality of buffer circuits at different points in time. The plurality of buffer circuits include clock regeneration circuits to regenerate a clock signal received from the module control device and to provide regenerated clock signals to respective groups of memory devices.

公开(公告)号：US20190295675A1

公开(公告)日：2019-09-26

申请号：US16286246

申请日：2019-02-26

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Soonju Choi

IPC: G11C29/10 ,  G11C29/12

Abstract: A memory module is operable in a computer system to communicate data with a system memory controller via a system memory bus. The memory module comprises a plurality of memory devices mounted on a circuit board, a data module mounted on the circuit board and coupled between the plurality of memory devices and the system memory bus, and a control circuit mounted on the circuit board and coupled to the data module, the plurality of memory devices, and the system memory bus. The data module includes a plurality of data handlers in a plurality of integrated circuits. The memory module is operable in any of a plurality of modes, including a first mode and a second mode. The plurality of memory devices in the first mode is accessed by the system memory controller for normal memory read or write operations. The plurality of memory devices in the second mode communicate data signals with the data module while the memory module is not being accessed by the system memory controller for normal memory read or write operations.

公开(公告)号：US10380022B2

公开(公告)日：2019-08-13

申请号：US14536588

申请日：2014-11-07

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Chi She Chen ,  Jeffery C. Solomon ,  Mario Jesus Martinez ,  Hao Le ,  Soon J. Choi

IPC: G06F5/10 ,  G06F12/0871 ,  G06F3/06 ,  G06F12/0897 ,  G06F13/28

Abstract: A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the C/A bus. The module controller is configured to control intra-module data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller is further configured to monitor C/A signals on the C/A bus and schedule the intra-module data transfers in accordance with the C/A signals so that the intra-module data transfers do not conflict with accesses to the volatile memory subsystem by the memory controller.

公开(公告)号：US10025731B1

公开(公告)日：2018-07-17

申请号：US14715491

申请日：2015-05-18

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Jeffrey C. Solomon ,  Mario Jesus Martinez ,  Chi-She Chen

IPC: G06F12/00 ,  G06F13/16 ,  G11C5/02 ,  G11C5/06 ,  G11C8/18 ,  G06F13/40

Abstract: Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.

公开(公告)号：US09426916B1

公开(公告)日：2016-08-23

申请号：US13964103

申请日：2013-08-11

Applicant: Netlist, Inc.

Inventor： Jayesh R. Bhakta ,  Son H. Nguyen

IPC: G11C5/02 ,  H05K7/06 ,  G11C8/12

CPC classification number: H05K7/06 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C8/12

Abstract: A multi-rank memory module is operable in a memory system with a memory controller. The memory module according to one embodiment comprises at least one module board, memory devices organized in three ranks, and at least one register device providing control/address signals to the memory devices. Arrangement of the ranks on the at least one module board are made to balance memory device loadings on the C/A signals, and data/strobe signal hubs are designed to provide better alignment of different data bits in a data signal and to reduce reflection from discrete components disposed near an edge of the module board, resulting in improved signal quality and integrity.

Abstract translation: 多级存储器模块可在具有存储器控制器的存储器系统中操作。 根据一个实施例的存储器模块包括至少一个模块板，以三个等级组织的存储器件，以及向存储器件提供控制/地址信号的至少一个寄存器器件。 使至少一个模块板上的排列布置为平衡C / A信号上的存储器件负载，并且数据/选通信号集线器被设计为提供数据信号中不同数据位的更好对准并减少来自 设置在模块板边缘附近的分立部件，从而提高了信号质量和完整性。

公开(公告)号：US20160162404A1

公开(公告)日：2016-06-09

申请号：US14445035

申请日：2014-07-28

Applicant: NETLIST, INC.

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G06F12/08

CPC classification number: G06F12/0802 ,  G11C5/04 ,  G11C7/1066 ,  G11C7/1093 ,  G11C29/023 ,  G11C29/028

Abstract: A memory module is operatable in a memory system with a memory controller. The memory module comprises a module control device to receive command signals from the memory controller and to output module C/A signals and data buffer control signals. The module C/A signals are provided to memory devices organized in groups, each group including at least one memory device, while the data buffer control signals are provided to a plurality of buffer circuits to control data paths in the buffer circuits, a respective buffer circuit corresponding to a respective group of memory devices. The plurality of buffer circuits are distributed across a surface of the memory module such that each data buffer control signal arrives at the plurality of buffer circuits at different points in time. The plurality of buffer circuits include clock regeneration circuits to regenerate a clock signal received from the module control device and to provide regenerated clock signals to respective groups of memory devices.33

Abstract translation: 存储器模块可在具有存储器控制器的存储器系统中操作。 存储器模块包括一个模块控制装置，用于从存储器控制器接收命令信号并输出​​模块C / A信号和数据缓冲器控制信号。 将模块C / A信号提供给组织组织的存储器件，每个组包括至少一个存储器件，同时将数据缓冲器控制信号提供给多个缓冲器电路以控制缓冲器电路中的数据路径，相应的缓冲器 电路对应于各组存储器件。 多个缓冲电路分布在存储器模块的表面上，使得每个数据缓冲器控制信号在不同的时间点到达多个缓冲电路。 多个缓冲电路包括时钟再生电路，用于再生从模块控制装置接收到的时钟信号，并将再生的时钟信号提供给各组存储器件。 33

公开(公告)号：US20160034408A1

公开(公告)日：2016-02-04

申请号：US14846993

申请日：2015-09-07

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G06F13/28 ,  G06F1/10 ,  G06F3/06 ,  G06F13/40

CPC classification number: G06F13/1673 ,  G06F1/10 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F13/1642 ,  G06F13/28 ,  G06F13/4027 ,  G11C5/04 ,  G11C7/1006 ,  G11C7/1066 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/20 ,  G11C8/12 ,  G11C8/18 ,  G11C16/00 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/0407

Abstract: A memory module is operatable in a memory system with a memory controller. The memory module comprises a module control device to receive command signals from the memory controller and to output module command signals and module control signals. The module command signals are provided to memory devices organized in groups, each group including at least one memory device, while the module control signals are provided to a plurality of buffer circuits to control data paths in the buffer circuits. The plurality of buffer circuits are associated with respective groups of memory devices and are distributed across a surface of the memory module such that each module control signal arrives at the plurality of buffer circuits at different points in time. The plurality of buffer circuits are configured to align read data signals received from the memory devices such that the read data signals are transmitted to the memory controller from the memory module substantially aligned with each other and in accordance with a read latency parameter of the memory system.

Abstract translation: 存储器模块可在具有存储器控制器的存储器系统中操作。 存储器模块包括一个模块控制装置，用于从存储器控制器接收命令信号并输出​​模块命令信号和模块控制信号。 将模块命令信号提供给以组为单位的存储器件，每个组包括至少一个存储器件，同时将模块控制信号提供给多个缓冲电路以控制缓冲电路中的数据路径。 多个缓冲电路与各组存储器件相关联，并且分布在存储器模块的表面上，使得每个模块控制信号在不同的时间点到达多个缓冲电路。 多个缓冲电路被配置为对从存储器件接收到的读取数据信号进行对准，使得读取的数据信号从存储器模块传输到存储器模块，该存储器模块基本上彼此对齐，并且根据存储器系统的读延迟参数 。

公开(公告)号：US20140040568A1

公开(公告)日：2014-02-06

申请号：US13970606

申请日：2013-08-20

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G06F12/00

CPC classification number: G06F12/00 ,  G11C5/025 ,  G11C5/04 ,  G11C5/066 ,  G11C8/12

Abstract: A memory module is operable to communicate with a memory controller via a data bus and a control/address bus and comprises a module board; a plurality of memory devices mounted on the module board; and multiple sets of data pins along an edge of the module board. Each respective set of the multiple sets of data pins is operatively coupled to a respective set of multiple sets of data lines in the data bus. The memory module further comprises a control circuit configured to receive control/address information from the memory controller via the control/address bus and to produce module control signals. The memory module further comprises a plurality of buffer circuits each being disposed proximate to and electrically coupled to a respective set of the multiple sets of data pins. Each buffer circuit is configured to respond to the module control signals by enabling data communication between the memory controller and at least one first memory device among the plurality of memory devices and by isolating at least one second memory device among the plurality of memory devices from the memory controller.

Abstract translation: 存储器模块可操作以经由数据总线和控制/地址总线与存储器控制器通信，并且包括模块板; 安装在模块板上的多个存储器件; 以及沿着模块板边缘的多组数据引脚。 多组数据引脚的每个相应组可操作地耦合到数据总线中相应的多组数据线。 存储器模块还包括控制电路，配置为经由控制/地址总线从存储器控制器接收控制/地址信息并产生模块控制信号。 存储器模块还包括多个缓冲电路，每个缓冲电路被设置为接近并电耦合到多组数据引脚的相应组。 每个缓冲电路被配置为通过使存储器控制器与多个存储器件中的至少一个第一存储器件之间的数据通信并且通过将多个存储器件中的至少一个第二存储器件与 内存控制器