公开(公告)号：US10985048B2

公开(公告)日：2021-04-20

申请号：US16732367

申请日：2020-01-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chi-Ting Wu ,  Chin-Hung Chen ,  Yu-Hsiang Lin

IPC: H01L21/762 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer on the first gate structure; removing the first gate structure to form a first recess; and forming a dielectric layer in the first recess.

公开(公告)号：US10347526B1

公开(公告)日：2019-07-09

申请号：US15951683

申请日：2018-04-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chi-Ting Wu ,  Chin-Hung Chen ,  Yu-Hsiang Lin

IPC: H01L21/768 ,  H01L23/485 ,  H01L23/532

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a gate structure, and a conductive element. The gate structure is on the substrate. The gate structure includes a gate electrode and a cap layer on the gate electrode. The conductive element is adjoined with an outer surface of the gate structure. The conductive element includes a lower conductive portion and an upper conductive portion electrically connected on the lower conductive portion and adjoined with the cap layer. The lower conductive portion and the upper conductive portion have an interface therebetween. The interface is below an upper surface of the cap layer.

公开(公告)号：US20190172752A1

公开(公告)日：2019-06-06

申请号：US15830008

申请日：2017-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Chun-Ya Chiu ,  Chin-Hung Chen ,  Chi-Ting Wu ,  Yu-Hsiang Lin

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/768 ,  H01L23/535 ,  H01L27/088 ,  H01L29/49

CPC classification number: H01L21/823475 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/823468 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure and a second gate structure on a substrate and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure into a first metal gate and the second gate structure into a second metal gate; removing part of the ILD layer between the first metal gate and the second metal gate to form a recess; forming a first spacer and a second spacer in the a recess; performing a first etching process to form a first contact hole; and performing a second etching process to extend the first contact hole into a second contact hole.

公开(公告)号：US20240395909A1

公开(公告)日：2024-11-28

申请号：US18791454

申请日：2024-08-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Hung Chen ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Chia-Jung Hsu ,  Yu-Hsiang Lin

IPC: H01L29/66 ,  H01L21/033 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/06 ,  H01L27/088 ,  H01L27/12 ,  H01L29/78

Abstract: A method for fabricating semiconductor device includes: forming a first semiconductor layer and an insulating layer on a substrate; removing the insulating layer and the first semiconductor layer to form openings; forming a second semiconductor layer in the openings; and patterning the second semiconductor layer, the insulating layer, and the first semiconductor layer to form fin-shaped structures.

公开(公告)号：US11990507B2

公开(公告)日：2024-05-21

申请号：US17403578

申请日：2021-08-16

Applicant: United Microelectronics Corp.

Inventor： Chin-Hung Chen ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Chun-Ya Chiu ,  Chia-Jung Hsu ,  Yu-Hsiang Lin

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L29/1095 ,  H01L29/7816

Abstract: A high voltage transistor structure including a substrate, a first isolation structure, a second isolation structure, a gate structure, a first source and drain region, and a second source and drain region is provided. The first isolation structure and the second isolation structure are disposed in the substrate. The gate structure is disposed on the substrate, at least a portion of the first isolation structure, and at least a portion of the second isolation structure. The first source and drain region and the second source and drain region are located in the substrate on two sides of the first isolation structure and the second isolation structure. The depth of the first isolation structure is greater than the depth of the second isolation structure.

公开(公告)号：US11901239B2

公开(公告)日：2024-02-13

申请号：US18104307

申请日：2023-02-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chi-Ting Wu ,  Chin-Hung Chen ,  Yu-Hsiang Lin

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649

Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.

公开(公告)号：US20230268346A1

公开(公告)日：2023-08-24

申请号：US17700475

申请日：2022-03-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ya Chiu ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Lin ,  Chien-Ting Lin ,  Chia-Jung Hsu ,  Chin-Hung Chen

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/31053 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate having a high-voltage (HV) region and a low-voltage (LV) region; forming a base on the HV region and fin-shaped structures on the LV region; forming a first insulating around the fin-shaped structures; removing the base, the first insulating layer, and part of the fin-shaped structures to form a first trench in the HV region and a second trench in the LV region; forming a second insulating layer in the first trench and the second trench; and planarizing the second insulating layer to form a first shallow trench isolation (STI) on the HV region and a second STI on the LV region.

公开(公告)号：US11721591B2

公开(公告)日：2023-08-08

申请号：US17338666

申请日：2021-06-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chi-Ting Wu ,  Chin-Hung Chen ,  Yu-Hsiang Lin

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer around the first gate structure; transforming the first gate structure into a first metal gate; removing the first metal gate to form a first recess; and forming a dielectric layer in the first recess.

公开(公告)号：US20230197710A1

公开(公告)日：2023-06-22

申请号：US17585582

申请日：2022-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Lin ,  Chien-Ting Lin ,  Chia-Jung Hsu ,  Chun-Ya Chiu ,  Chin-Hung Chen

IPC: H01L27/02 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/0266 ,  H01L29/41791 ,  H01L29/7851 ,  H01L29/66795 ,  H01L29/0653

Abstract: A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is lower than a top surface of the fin-shaped structure.

公开(公告)号：US20230047580A1

公开(公告)日：2023-02-16

申请号：US17403578

申请日：2021-08-16

Applicant: United Microelectronics Corp.

Inventor： Chin-Hung Chen ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Chun-Ya Chiu ,  Chia-Jung Hsu ,  Yu-Hsiang Lin

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78

Abstract: A high voltage transistor structure including a substrate, a first isolation structure, a second isolation structure, a gate structure, a first source and drain region, and a second source and drain region is provided. The first isolation structure and the second isolation structure are disposed in the substrate. The gate structure is disposed on the substrate, at least a portion of the first isolation structure, and at least a portion of the second isolation structure. The first source and drain region and the second source and drain region are located in the substrate on two sides of the first isolation structure and the second isolation structure. The depth of the first isolation structure is greater than the depth of the second isolation structure.