公开(公告)号：US20240099154A1

公开(公告)日：2024-03-21

申请号：US18515273

申请日：2023-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Si-Han Tsai ,  Dong-Ming Wu ,  Chen-Yi Weng ,  Ching-Hua Hsu ,  Ju-Chun Fan ,  Yi-Yu Lin ,  Che-Wei Chang ,  Po-Kai Hsu ,  Jing-Yin Jhang

IPC: H10N50/10 ,  G11C11/16 ,  H01F10/32 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N50/10 ,  G11C11/161 ,  H01F10/3254 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.

公开(公告)号：US20240074328A1

公开(公告)日：2024-02-29

申请号：US18502109

申请日：2023-11-06

Applicant: United Microelectronics Corp.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Yi-Wei Tseng ,  Chin-Yang Hsieh ,  Jing-Yin Jhang ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  I-Ming Tseng ,  Yu-Ping Wang

IPC: H10N50/80 ,  G11C5/06 ,  G11C11/16 ,  H01L29/82 ,  H10N50/01 ,  H10N50/10

CPC classification number: H10N50/80 ,  G11C5/06 ,  G11C11/16 ,  G11C11/161 ,  H01L29/82 ,  H10N50/01 ,  H10N50/10 ,  G11C2211/5615 ,  H10B61/00

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.

公开(公告)号：US11895926B2

公开(公告)日：2024-02-06

申请号：US17088531

申请日：2020-11-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Ju-Chun Fan ,  Ching-Hua Hsu ,  Yi-Yu Lin ,  Hung-Yueh Chen

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.

公开(公告)号：US11882769B2

公开(公告)日：2024-01-23

申请号：US17239667

申请日：2021-04-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Bo-Yun Huang ,  Wen-Wen Zhang ,  Kun-Chen Ho

IPC: H01L43/02 ,  H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A magnetoresistive random access memory (MRAM) structure is provided in the present invention, including multiple MRAM cells, and an atomic layer deposition dielectric layer between and at outer sides of the MRAM cells, wherein the material of top electrode layer is titanium nitride, and the nitrogen percentage is greater than titanium percentage and further greater than oxygen percentage in the titanium nitride, and the nitrogen percentage gradually increases inward from the top surface of top electrode layer to a depth and then start to gradually decrease to a first level and then remains constant, and the titanium percentage gradually decreases inward from the top surface of top electrode layer to the depth and then start to gradually increase to a second level and then remains constant.

公开(公告)号：US20240023455A1

公开(公告)日：2024-01-18

申请号：US17887486

申请日：2022-08-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/02

Abstract: A method for fabricating semiconductor device includes the steps of first forming a bottom electrode on a substrate, forming a magnetic tunneling junction (MTJ) on the bottom electrode, and then forming a cap layer on the MTJ. Preferably, the formation of the cap layer could be accomplished by the following steps: (a) forming a first metal layer on the MTJ; (b) forming a second metal layer on the first metal layer; and (c) performing an oxidation process.

公开(公告)号：US20230354715A1

公开(公告)日：2023-11-02

申请号：US18215162

申请日：2023-06-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Tai-Cheng Hou ,  Wei-Xin Gao ,  Fu-Yu Tsai ,  Chin-Yang Hsieh ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Bin-Siang Tsai ,  Kun-Ju Li ,  Chih-Yueh Li ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Yu-Tsung Lai ,  Wei-Hao Huang

IPC: H10N50/10 ,  H01L21/768 ,  H01L21/762 ,  H10N50/80

CPC classification number: H10N50/10 ,  H01L21/76802 ,  H01L21/762 ,  H10N50/80 ,  H10N35/01

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.

公开(公告)号：US20230292627A1

公开(公告)日：2023-09-14

申请号：US18200592

申请日：2023-05-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Ju-Chun Fan ,  Yi-Yu Lin ,  Ching-Hua Hsu ,  Hung-Yueh Chen

IPC: H10N50/10 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N50/10 ,  H10B61/22 ,  H10N50/80 ,  H10N50/85

Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.

公开(公告)号：US11737370B2

公开(公告)日：2023-08-22

申请号：US17141194

申请日：2021-01-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Tai-Cheng Hou ,  Wei-Xin Gao ,  Fu-Yu Tsai ,  Chin-Yang Hsieh ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Bin-Siang Tsai ,  Kun-Ju Li ,  Chih-Yueh Li ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Yu-Tsung Lai ,  Wei-Hao Huang

IPC: H01L41/47 ,  H10N50/10 ,  H01L21/768 ,  H01L21/762 ,  H10N50/80 ,  H10N35/01

CPC classification number: H10N50/10 ,  H01L21/762 ,  H01L21/76802 ,  H10N50/80 ,  H10N35/01

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.

公开(公告)号：US11665973B2

公开(公告)日：2023-05-30

申请号：US17736069

申请日：2022-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Hung-Yueh Chen ,  Yu-Ping Wang

IPC: H10N50/01

CPC classification number: H10N50/01 ,  H10N50/80 ,  H10B61/00 ,  H10N50/85

Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a top electrode on the MTJ stack; performing a first patterning process to remove the MTJ stack for forming a first MTJ; forming a first inter-metal dielectric (IMD) layer around the first MTJ; and performing a second patterning process to remove the first MTJ for forming a second MTJ and a third MTJ.

公开(公告)号：US11637233B2

公开(公告)日：2023-04-25

申请号：US17086447

申请日：2020-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Si-Han Tsai ,  Che-Wei Chang ,  Po-Kai Hsu ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Ju-Chun Fan ,  Ching-Hua Hsu ,  Yi-Yu Lin ,  Hung-Yueh Chen

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  H01L43/10

Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.