公开(公告)号：US10700161B2

公开(公告)日：2020-06-30

申请号：US16159726

申请日：2018-10-15

Applicant: Unimicron Technology Corp.

Inventor： Yu-Hua Chen ,  Fu-Yang Chen ,  Chun-Hsien Chien ,  Chien-Chou Chen ,  Wei-Ti Lin

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/498 ,  H01L23/15 ,  H01L23/532

Abstract: A manufacturing method of a substrate structure includes the following steps. A first build-up circuit structure is formed. At least one copper pillar is formed on the first build-up circuit structure. A dielectric layer is formed on the first build-up circuit structure, and the dielectric layer wraps the copper pillar. A second build-up circuit structure and a capacitive element are formed on the dielectric layer. In particular, the second build-up circuit structure and the first build-up circuit structure are respectively located at two opposite sides of the dielectric layer. The capacitive element is disposed in a capacitive element setting region within the second build-up circuit structure. The copper pillar penetrates the dielectric layer and is electrically connected to the second build-up circuit structure and the first build-up circuit structure. A substrate structure obtained by the manufacturing method of the substrate structure is provided.

公开(公告)号：US10461146B1

公开(公告)日：2019-10-29

申请号：US16151351

申请日：2018-10-04

Applicant: Unimicron Technology Corp.

Inventor： Wen-Liang Yeh ,  Chun-Hsien Chien ,  Chien-Chou Chen ,  Cheng-Hui Wu

IPC: H01L21/02 ,  H01L49/02 ,  H01L23/00 ,  H01L23/522

Abstract: A package structure includes a substrate, a metal-insulator-metal capacitor, a circuit redistribution structure, and a chip. The metal-insulator-metal capacitor is disposed over the substrate and includes a first electrode, a second electrode, and an insulating layer. The circuit redistribution structure is disposed over the metal-insulator-metal capacitor and includes a first circuit redistribution layer and a second circuit redistribution layer. The first circuit redistribution layer includes a first wire electrically connected to the first electrode and a second wire electrically connected to the second electrode. The second circuit redistribution layer is disposed on the first circuit redistribution layer and includes a third wire electrically connected to the first wire and a fourth wire electrically connected to the second wire. The chip is disposed over the circuit redistribution structure and electrically connected to the third wire and the fourth wire.

公开(公告)号：US09860980B1

公开(公告)日：2018-01-02

申请号：US15273672

申请日：2016-09-22

Applicant: Unimicron Technology Corp.

Inventor： Yu-Chung Hsieh ,  Chun-Hsien Chien ,  Wei-Ti Lin ,  Yu-Hua Chen

IPC: H05K1/02 ,  H05K1/03

CPC classification number: H05K1/0306 ,  H05K1/0271 ,  H05K3/0052 ,  H05K3/4605 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/0175 ,  H05K2201/068 ,  H05K2201/09845

Abstract: A circuit board element includes a glass substrate, a first dielectric layer, and a first patterned metal layer. The glass substrate has an edge. The first dielectric layer is disposed on the glass substrate and has a central region and an edge region. The edge region is in contact with the edge of the glass substrate, and the thickness of the central region is greater than the thickness of the edge region. The first patterned metal layer is disposed on the glass substrate and in the central region of the first dielectric layer.