Method and Apparatus for Detecting Data in Wireless Communication Networks

    公开(公告)号:US20170288902A1

    公开(公告)日:2017-10-05

    申请号:US15629181

    申请日:2017-06-21

    Abstract: An apparatus including a processor configured to receive a digital communication signal having a plurality of transmitted layers. The processor is configured to determine an estimated channel matrix based on the digital communication signal, determine a first estimated transmitted symbol vector and a mean square error matrix based on a linear analysis of the received digital communication signal. A first set of bit LLR are determined based on a LMMSE type detector and a second set of bit LLR are determined based on a novel simplified tree search process. The two sets of bit LLR are then combined and used to detect the data in the received communication signal. The simplified tree search process uses a specially formed channel shortening process to determine a set of shortened channel correlation matrices that allow the second set of bit LLR to be determined using an alternative marginalized tree search process.

    ERROR CORRECTION CIRCUIT AND OPTICAL TRANSMISSION SYSTEM

    公开(公告)号:US20170250780A1

    公开(公告)日:2017-08-31

    申请号:US15420807

    申请日:2017-01-31

    Abstract: An error correction circuit includes a first error correction circuit, a second error correction circuit and a controller. The first error correction circuit performs an error correction in a first correction scheme. The second error correction circuit performs an error correction in a second correction scheme. A correction performance of the second correction scheme is lower than a correction performance of the first correction scheme. The controller makes the first error correction circuit perform error correction of a received signal when a capacity of the received signal is smaller than or equal to a processing capacity of the first error correction circuit, and makes the first error correction circuit and the second error correction circuit perform error correction of the received signal when the capacity of the received signal is larger than the processing capacity of the first error correction circuit.

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