公开(公告)号：US20150037611A1

公开(公告)日：2015-02-05

申请号：US14380207

申请日：2013-02-20

Applicant: KYOCERA Corporation

Inventor： Tadashi Nagasawa ,  Katsura Hayashi

IPC: H05K1/03 ,  H05K3/46

CPC classification number: H05K1/036 ,  H05K3/3436 ,  H05K3/4602 ,  H05K3/4661 ,  H05K3/467 ,  H05K3/4673 ,  H05K2201/0175 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0269 ,  H05K2201/068

Abstract: A wiring board (3) according to an embodiment of the present invention includes an inorganic insulating layer (11A); a first resin layer (12A) on one main surface of the inorganic insulating layer (11A); a second resin layer (13A) on another main surface of the inorganic insulating layer (11A); and a conductive layer (8) partially on one main surface of the second resin layer (13A), the one main surface being on an opposite side to the inorganic insulating layer (11A). The inorganic insulating layer (11A) includes a plurality of first inorganic insulating particles (14) which are bound to each other at a part of each of the first inorganic insulating particles and gaps (G) surrounded by the plurality of first inorganic insulating particles (14). A part of the first resin layer (12A) and a part of the second resin layer (13A) are located inside the gaps (G).

Abstract translation: 根据本发明实施例的布线板（3）包括无机绝缘层（11A）; 在无机绝缘层（11A）的一个主表面上的第一树脂层（12A）; 在无机绝缘层（11A）的另一个主表面上的第二树脂层（13A）; 以及部分地在所述第二树脂层（13A）的一个主表面上的导电层（8），所述一个主表面与所述无机绝缘层（11A）相反。 无机绝缘层（11A）包括多个第一无机绝缘粒子（14），它们在由多个第一无机绝缘粒子包围的第一无机绝缘粒子和间隙（G）的一部分彼此结合 14）。 第一树脂层（12A）的一部分和第二树脂层（13A）的一部分位于间隙（G）的内部。

公开(公告)号：US20140284088A1

公开(公告)日：2014-09-25

申请号：US14354600

申请日：2012-09-28

Applicant: KYOCERA Corporation

Inventor： Kiyotaka Nakamura ,  Yoshio Ohashi ,  Kunihide Shikata

IPC: H05K1/09

CPC classification number: H05K1/09 ,  C04B41/009 ,  C04B41/52 ,  C04B41/90 ,  C04B2111/00405 ,  C04B2111/00844 ,  H01L23/15 ,  H01L23/3731 ,  H01L23/3735 ,  H01L23/3736 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K1/092 ,  H05K3/245 ,  H05K3/38 ,  H05K2201/0269 ,  H05K2201/0338 ,  H05K2201/035 ,  H05K2203/1126 ,  C04B35/00 ,  C04B35/10 ,  C04B35/185 ,  C04B35/48 ,  C04B35/581 ,  C04B35/584 ,  C04B41/4539 ,  C04B41/4572 ,  C04B41/5022 ,  C04B41/5127 ,  C04B41/5116 ,  C04B41/522 ,  C04B41/5155 ,  H01L2924/00

Abstract: A circuit board is provided with a metal wiring layer 12 on at least one principal surface of a ceramic sintered body 11, wherein the above-described metal wiring layer includes a first region 12a which is in contact with the principal surface and which contains a glass component and a second region 12b which is located on the first region 12a and which does not contain a glass component, the thickness of the first region 12a is 35% or more and 70% or less of the thickness of the metal wiring layer 12, and the average grain size in the first region 12a is smaller than the average grain size in the second region 12b.

Abstract translation: 电路板在陶瓷烧结体11的至少一个主面上设置有金属布线层12，其中上述金属布线层包括与主表面接触且包含玻璃的第一区域12a 第一区域12a和第二区域12b位于第一区域12a上并且不包含玻璃成分，第一区域12a的厚度为金属布线层12的厚度的35％以上且70％以下， 并且第一区域12a中的平均晶粒尺寸小于第二区域12b中的平均晶粒尺寸。

公开(公告)号：US20140161971A1

公开(公告)日：2014-06-12

申请号：US14183379

申请日：2014-02-18

Applicant: FUJIFILM CORPORATION

Inventor： Seishi KASAI

IPC: C09D11/00

CPC classification number: C09D11/52 ,  B41M5/0023 ,  H05K1/097 ,  H05K3/125 ,  H05K2201/0269 ,  H05K2203/1476

Abstract: A forming method of a conductive pattern including a base material and a pattern of a composition gradient layer in which the composition continuously changes from a metal to a resin in a thickness direction from the farthest side to the base material toward the nearest side to the base material, includes: ejecting at least two kinds of ink compositions of an ink composition containing a metal and an ink composition containing a compound capable of being cured with active energy ray, or a polymer or oligomer, onto the base material by an inkjet method to fabricate the composition gradient layer.

Abstract translation: 一种导电图案的形成方法，其包括基材和组合物梯度层的图案，其中组合物从最远侧到基底至最靠近基底的从金属到树脂在厚度方向上连续变化 材料包括：通过喷墨方法将含有金属的油墨组合物和含有能够用活性能量射线固化的化合物或聚合物或低聚物的油墨组合物的至少两种油墨组合物喷射到基材上 制作组成梯度层。

公开(公告)号：US20120301825A1

公开(公告)日：2012-11-29

申请号：US13569715

申请日：2012-08-08

Applicant: Takahiro YOSHIDA ,  Shouji Minegishi ,  Masao Arima

Inventor： Takahiro YOSHIDA ,  Shouji Minegishi ,  Masao Arima

IPC: G03F7/004

CPC classification number: G03F7/095 ,  G03F7/0047 ,  H05K3/287 ,  H05K3/3452 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0269

Abstract: In a layered structure having at least a substrate and a photosensitive resin layer or cured film layer formed on the substrate and containing an inorganic filler, the content of the inorganic filler in the photosensitive resin layer or cured film layer is lower in a surface layer region away from the substrate than in other region, so that a linear thermal expansion coefficient of the layer as a whole is maintained as low as possible. Preferably, the photosensitive resin layer or cured film layer comprises at least two layers having different inorganic filler contents, wherein the inorganic filler content in the layer on the surface side away from the substrate is lower than the inorganic filler content in the other layer. A photosensitive dry film containing the photosensitive resin layer is suitable for use as a solder resist or an interlayer resin insulation layer of a printed wiring board.

Abstract translation: 在至少具有基板和形成在基板上并含有无机填料的感光性树脂层或固化膜层的分层结构中，感光性树脂层或固化膜层中的无机填料的含量在表面层区域 远离衬底而不是在其他区域，使得整个层的线性热膨胀系数保持尽可能低。 优选地，感光性树脂层或固化膜层包含至少两层具有不同无机填料含量的层，其中离开基材的表面侧的层中的无机填料含量低于另一层中的无机填料含量。 含有感光性树脂层的感光性干膜适合用作印刷电路板的阻焊剂或层间树脂绝缘层。

公开(公告)号：US08241760B2

公开(公告)日：2012-08-14

申请号：US12440986

申请日：2006-09-14

Applicant: Toshiaki Chuma

Inventor： Toshiaki Chuma

IPC: B32B15/04 ,  B32B15/20 ,  H05K3/00 ,  B23K20/00 ,  H01R4/00 ,  H01R4/02

CPC classification number: H05K3/4617 ,  B23K1/0016 ,  B23K35/001 ,  B23K35/0238 ,  B23K35/262 ,  B23K35/3613 ,  B23K35/3618 ,  B23K35/362 ,  C25D5/48 ,  H05K3/341 ,  H05K3/3463 ,  H05K2201/0269 ,  H05K2203/1476 ,  Y02P70/613 ,  Y10T29/49149 ,  Y10T428/12708 ,  Y10T428/12715 ,  Y10T428/12903

Abstract: A joint structure of the present invention includes a conductive member containing copper as a major component thereof, an electrode member containing copper as a major component thereof, and a joint portion formed by fusion welding the conductive member and the electrode member with a brazing material containing tin as a major component thereof and containing substantially no copper, wherein the amount of copper atoms contained in the alloy in the central part of the joint portion is higher than that in the outer circumference part.

Abstract translation: 本发明的接合结构包括以铜为主要成分的导电构件，以铜为主要成分的电极构件和通过将导电构件和电极构件与含有 锡作为其主要组分并且基本上不含铜，其中在接合部分的中心部分中合金中包含的铜原子的量高于外周部分。

公开(公告)号：US08163381B2

公开(公告)日：2012-04-24

申请号：US12256665

申请日：2008-10-23

Applicant: Pui-Yan Lin ,  Govindasamy Paramasivam Rajendran ,  George Elias Zahr

Inventor： Pui-Yan Lin ,  Govindasamy Paramasivam Rajendran ,  George Elias Zahr

IPC: H05K1/02

CPC classification number: H01L23/49894 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0271 ,  H05K3/108 ,  H05K3/4661 ,  H05K2201/0209 ,  H05K2201/0269 ,  H05K2201/068 ,  Y10T29/49126 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/24917 ,  Y10T428/25 ,  Y10T428/2998 ,  Y10T428/31515 ,  Y10T428/31518 ,  Y10T428/31529 ,  H01L2924/00

Abstract: Provided, are multi-layer chip carriers comprising an asymmetric cross-linked polymeric dielectric film, and processes for making the chip carriers.

Abstract translation: 提供了包括不对称交联聚合物电介质膜的多层芯片载体，以及用于制造芯片载体的工艺。

公开(公告)号：US08053682B2

公开(公告)日：2011-11-08

申请号：US12467542

申请日：2009-05-18

Applicant: Yun Hwi Park ,  Bong Gyun Kim ,  Yoon Hyuck Choi

Inventor： Yun Hwi Park ,  Bong Gyun Kim ,  Yoon Hyuck Choi

IPC: H05K1/11

CPC classification number: H05K3/4061 ,  H05K1/0242 ,  H05K3/4629 ,  H05K2201/0269 ,  H05K2201/096 ,  H05K2203/082 ,  Y10T428/24322 ,  Y10T428/24926

Abstract: There is provided a multilayer ceramic substrate including a conductive via of a dual-layer structure capable of preventing loss in electrical conductivity and signal. The multilayer ceramic substrate includes: a plurality of dielectric layers; and a circuit pattern part formed on at least a portion of the dielectric layers, the circuit pattern part including at least one conductive via and conductive pattern, wherein the at least one conductive via comprises an outer peripheral portion and an inner peripheral portion, the outer peripheral portion formed along an inner wall of a via hole extending through the dielectric layers and formed of a first conductive material containing a metal, and the inner peripheral portion filled in the outer peripheral portion and formed of a second conductive material having a shrinkage initiation temperature higher than a shrinkage initiation temperature of the first conductive material.

Abstract translation: 提供了一种包括能够防止导电性和信号损失的双层结构的导电通孔的多层陶瓷基板。 多层陶瓷基板包括：多个电介质层; 以及形成在所述电介质层的至少一部分上的电路图形部分，所述电路图形部分包括至少一个导电通路和导电图案，其中所述至少一个导电通孔包括外周部分和内周部分， 沿着贯穿电介质层的通路孔的内壁形成的周边部分，并且由包含金属的第一导电材料形成，并且内周部分填充在外周部分中，并由具有收缩起始温度的第二导电材料形成 高于第一导电材料的收缩起始温度。

公开(公告)号：US20100006335A1

公开(公告)日：2010-01-14

申请号：US12548661

申请日：2009-08-27

Applicant: Masato NOMIYA ,  Satoshi ASAKURA ,  Tatsuya UEDA ,  Akira BABA

Inventor： Masato NOMIYA ,  Satoshi ASAKURA ,  Tatsuya UEDA ,  Akira BABA

IPC: H05K1/11 ,  B32B17/06 ,  B22F3/10 ,  C04B35/64

CPC classification number: H05K3/38 ,  B32B18/00 ,  C04B2235/36 ,  C04B2237/341 ,  C04B2237/343 ,  C04B2237/345 ,  C04B2237/346 ,  C04B2237/348 ,  C04B2237/62 ,  C04B2237/68 ,  C04B2237/704 ,  H05K1/0306 ,  H05K3/4061 ,  H05K3/4611 ,  H05K3/4629 ,  H05K3/4688 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0269 ,  Y10T428/12056 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: In a multilayer ceramic substrate manufactured by a non-shrinking process, a bonding strength of an external conductive film formed on a primary surface of the multilayer ceramic substrate is increased. After a laminate of a multilayer ceramic substrate is formed from first ceramic layers and second shrinkage suppressing ceramic layers, and an underlayer is formed along one primary surface of the multilayer ceramic substrate, an external conductive film is formed on the underlayer. A non-sintering ceramic material powder in a non-sintered state is included in both the external conductive film and the underlayer, and this non-sintering ceramic material powder is fixed due to diffusion of a glass component from the first ceramic layers.

Abstract translation: 在通过非收缩工艺制造的多层陶瓷基板中，形成在多层陶瓷基板的主表面上的外部导电膜的接合强度增加。 在由第一陶瓷层和第二收缩抑制陶瓷层形成多层陶瓷基板的层压体之后，沿着多层陶瓷基板的一个主面形成下层，在底层上形成外部导电膜。 外部导电膜和底层都包含非烧结状态的非烧结陶瓷材料粉末，由于来自第一陶瓷层的玻璃成分的扩散，这种非烧结陶瓷材料粉末被固定。

公开(公告)号：US20090145642A1

公开(公告)日：2009-06-11

申请号：US12303513

申请日：2007-06-06

Applicant: Yoshirou Kuromitsu ,  Hiroya Ishizuka ,  Hiroshi Miyata ,  Takeshi Kitahara ,  Hiroshi Tonomura

Inventor： Yoshirou Kuromitsu ,  Hiroya Ishizuka ,  Hiroshi Miyata ,  Takeshi Kitahara ,  Hiroshi Tonomura

IPC: H05K1/03 ,  H05K3/10

CPC classification number: H01L23/3736 ,  H01L23/3735 ,  H01L23/473 ,  H01L24/32 ,  H01L2224/32225 ,  H05K1/09 ,  H05K3/38 ,  H05K2201/0269 ,  Y10T29/49124

Abstract: A power element mounting substrate including a circuit layer brazed to a surface of a ceramic plate, and a power element soldered to a front surface of the circuit layer, wherein the circuit layer is constituted using an Al alloy with an average purity of more than or equal to 98.0 wt % and less than or equal to 99.9 wt %, Fe concentration of the circuit layer at a side of a surface to be brazed to the ceramic plate is less than 0.1 wt %, and Fe concentration of the circuit layer at a side of the surface opposite to the surface to be brazed is more than or equal to 0.1 wt %.

Abstract translation: 一种功率元件安装基板，包括钎焊到陶瓷板的表面的电路层和焊接到电路层的前表面的功率元件，其中电路层使用平均纯度大于或等于 等于98.0重量％且小于或等于99.9重量％时，要钎焊到陶瓷板的表面侧的电路层的Fe浓度小于0.1重量％，电路层的铁浓度在 与钎焊表面相对的表面的一侧大于或等于0.1重量％。

公开(公告)号：US20080213605A1

公开(公告)日：2008-09-04

申请号：US11999665

申请日：2007-12-06

Applicant: Gary C. Briney ,  Brian C. Auman ,  Christopher J. Milasincic

Inventor： Gary C. Briney ,  Brian C. Auman ,  Christopher J. Milasincic

IPC: B32B27/20

CPC classification number: B32B27/34 ,  B32B27/20 ,  H05K1/0346 ,  H05K1/036 ,  H05K1/0373 ,  H05K2201/0154 ,  H05K2201/0209 ,  H05K2201/0269 ,  Y10T428/31504 ,  Y10T428/31721

Abstract: The invention is directed to substrates for electronic circuitry. The substrates of the invention have a first polyimide layer having a functional filler and a second polyimide layer having a functional filler. The first layer is non-identical to the second layer, and a surface of the first layer is in contact with and is directly bonded to a surface of the second layer. Filler from each layer extends into the interface between the two layers, and a plurality of covalent bonds are present between the first and second functional layers that chemically bond the two layers together to provide a reliable, predictable multifunctional substrate for electronic circuitry with improved performance relative to polyimide layers bonded together by an adhesive.