公开(公告)号：US08553426B2

公开(公告)日：2013-10-08

申请号：US13304415

申请日：2011-11-25

Applicant: Tsung-Sheng Huang

Inventor： Tsung-Sheng Huang

IPC: H05K7/00

CPC classification number: H05K1/0265 ,  H05K1/0298 ,  H05K3/429 ,  H05K2201/0352 ,  H05K2201/09618 ,  H05K2201/09672 ,  H05K2201/09727 ,  H05K2201/0979

Abstract: A circuit board includes a plurality of conductive layers, at least one group of vias, a number of second vias, at least one power supply element, and at least one electronic element. Each conductive layer includes a conductive portion. Both the first vias and the second vias are defined through the conductive layers and electrically connected each conductive layers. The at least one group of first vias surrounds the at least one power supply element. The second vias are arranged along the side of the conductive portion, and positioned between the power supply element and the electronic element. Current from a power supply element flows to the inner conductive layers through the group of surrounding first vias. Current transmission on each conductive layer continuously flows to another conductive layer having a lower resistance through the second vias during transmission.

Abstract translation: 电路板包括多个导电层，至少一组通孔，多个第二通孔，至少一个电源元件和至少一个电子元件。 每个导电层包括导电部分。 第一通孔和第二通孔都通过导电层定义并电连接每个导电层。 所述至少一组第一通孔围绕所述至少一个电源元件。 第二通孔沿着导电部分的侧面布置，并且位于电源元件和电子元件之间。 来自电源元件的电流通过一组周围的第一通孔流到内部导电层。 在传输期间，每个导电层上的电流传输通过第二通孔连续流动到具有较低电阻的另一导电层。

公开(公告)号：US20130241873A1

公开(公告)日：2013-09-19

申请号：US13839540

申请日：2013-03-15

Applicant: LG DISPLAY CO., LTD.

Inventor： SungChul KIM ,  Sujin KWON

IPC: H05K1/02 ,  G06F3/044 ,  G02F1/1333

CPC classification number: H05K1/0228 ,  G02F1/13338 ,  G02F1/13452 ,  G06F3/0412 ,  G06F3/0418 ,  G06F3/044 ,  H05K2201/09672

Abstract: Discussed is a Flexible Printed Circuit (FPC). The FPC includes a plurality of touch lines respectively connected to a plurality of touch electrode lines, a first film adhered to the touch lines, a second film overlapping the first film at an upper end surface of the first film and covering the touch lines, and a feedback compensation signal electrode adhered to a lower end surface of the first film, and receiving a feedback compensation signal for removing noise.

Abstract translation: 讨论了柔性印刷电路（FPC）。 FPC包括分别连接到多个触摸电极线的多个触摸线，粘附到触摸线的第一膜，在第一膜的上端表面处覆盖第一膜并覆盖触摸线的第二膜，以及 反馈补偿信号电极，粘附到第一膜的下端面，并且接收用于去除噪声的反馈补偿信号。

公开(公告)号：US20130215587A1

公开(公告)日：2013-08-22

申请号：US13674451

申请日：2012-11-12

Applicant: FUJITSU LIMITED

Inventor： Kenichi KAWAI

IPC: H05K1/11 ,  H05K7/06 ,  H05K1/18

CPC classification number: H05K1/115 ,  H05K1/0225 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/0298 ,  H05K1/116 ,  H05K1/181 ,  H05K7/06 ,  H05K2201/09672 ,  H05K2201/09718

Abstract: Provided is a multilayer wiring board including a plurality of signal layers and ground layers. The multilayer wiring board includes: a first differential wiring wired to a third signal layer; and a second differential wiring wired to a ninth signal layer disposed above the third signal layer. The multilayer wiring board includes a first differential signal via and a second differential signal via that are connected to the first differential wiring. The multilayer wiring board includes a third differential signal via which is connected to the second differential wiring and a stub of which is terminated above the third signal layer. The multilayer wiring board includes a fourth differential signal via which is connected to the second differential wiring and a stub of which is terminated above the third signal layer, the first differential wiring wired to pass between the fourth differential signal via and the third differential signal via.

Abstract translation: 提供了包括多个信号层和接地层的多层布线板。 多层布线板包括：布线到第三信号层的第一差分布线; 以及布线到设置在第三信号层上方的第九信号层的第二差分布线。 多层布线基板包括连接到第一差分布线的第一差分信号通孔和第二差分信号通孔。 多层布线板包括第三差分信号，经由该第三差分信号连接到第二差分布线，并且其短截线在第三信号层上方终止。 所述多层布线基板包括第四差分信号，所述第四差分信号经由其连接到所述第二差分布线，并且其短截线终止于所述第三信号层之上，所述第一差分布线经由所述第四差分信号通孔和所述第三差分信号经过 。

公开(公告)号：US20130168145A1

公开(公告)日：2013-07-04

申请号：US13626896

申请日：2012-09-26

Applicant: YING-TSO LAI ,  HSIAO-YUN SU

Inventor： YING-TSO LAI ,  HSIAO-YUN SU

IPC: H01G4/005 ,  H05K1/16

CPC classification number: H01G4/012 ,  H01G4/228 ,  H01G4/33 ,  H01G4/38 ,  H05K1/162 ,  H05K3/4644 ,  H05K2201/0191 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09672

Abstract: A capacitor includes at least two electrode layers opposite to each other and a dielectric layer positioned between the at least two electrode layers. The at least two electrode layers have opposite polarities. Each electrode layer includes a positive electrode and a negative electrode. The positive electrode includes a plurality of first coupling portions spaced substantially evenly and arranged in parallel. The negative electrode includes a plurality of second coupling portions spaced substantially evenly and arranged in parallel. The positive electrode and the negative electrode of each electrode layer are coplanar, and the plurality of first coupling portions interlace with the plurality of second coupling portions.

Abstract translation: 电容器包括彼此相对的至少两个电极层和位于所述至少两个电极层之间的电介质层。 至少两个电极层具有相反的极性。 每个电极层包括正极和负极。 正电极包括大致均匀间隔开并且平行布置的多个第一耦合部分。 负极包括大致均匀间隔开并且平行布置的多个第二联接部。 每个电极层的正电极和负电极是共面的，并且多个第一耦合部分与多个第二耦合部分交织。

公开(公告)号：US08467151B1

公开(公告)日：2013-06-18

申请号：US12785150

申请日：2010-05-21

Applicant: William D. Huber

Inventor： William D. Huber

IPC: G11B5/48

CPC classification number: G11B5/486 ,  G11B5/484 ,  H01P1/20345 ,  H01P3/081 ,  H05K1/0245 ,  H05K1/0248 ,  H05K1/025 ,  H05K2201/09245 ,  H05K2201/09254 ,  H05K2201/09672 ,  H05K2201/09727

Abstract: A disk drive is disclosed comprising a disk, a head actuated over the disk, a preamp, and an interconnect for coupling the head to the preamp. The interconnect comprises a first transmission line stacked with a second transmission line, and a dielectric between the first transmission line and second transmission line. The transmission lines form an approximation of at least one inductor/capacitor ladder network and an approximation of at least one inductor/capacitor lattice network. The lattice network comprises a first leg and a second leg, and a cross-over hub for interconnecting the first leg and the second leg.

Abstract translation: 公开了一种磁盘驱动器，其包括盘，在盘上致动的头，前置放大器和用于将头连接到前置放大器的互连。 互连包括堆叠有第二传输线的第一传输线和第一传输线与第二传输线之间的电介质。 传输线形成至少一个电感器/电容器梯形网络的近似值和至少一个电感器/电容器网格网络的近似值。 格子网络包括第一腿和第二腿，以及用于互连第一腿和第二腿的交叉毂。

公开(公告)号：US20130057276A1

公开(公告)日：2013-03-07

申请号：US13606486

申请日：2012-09-07

Applicant: Philippe Klein

Inventor： Philippe Klein

IPC: H01F5/00 ,  H02K21/26 ,  G01R33/00

CPC classification number: H05K1/165 ,  G01R33/0052 ,  G01R33/04 ,  G01R33/045 ,  G01R33/05 ,  H01F5/003 ,  H02K3/26 ,  H02K35/02 ,  H05K1/0239 ,  H05K3/46 ,  H05K2201/086 ,  H05K2201/09263 ,  H05K2201/09672 ,  H05K2201/097

Abstract: A printed circuit in which, in going from one end to another, a same conductive line is wound successively: around the first winding axis to form at least one half-turn of a first coil, then around the second winding axis to form at least one half-turn of a second coil, then around the first winding axis to form at least one half-turn of a first coil, then around the second winding axis to form at least one half-turn of a second coil.

Abstract translation: 一个印刷电路，其中从一端到另一端，相同的导电线依次缠绕：围绕第一卷绕轴线形成第一线圈的至少一个半圈，然后围绕第二绕组轴线形成，以形成至少 然后围绕第一绕组轴线形成第一线圈的至少一个半匝，然后围绕第二绕组轴线形成第二线圈的至少一个半匝。

公开(公告)号：US08367937B2

公开(公告)日：2013-02-05

申请号：US12549993

申请日：2009-08-28

Applicant: Voonyee Ho ,  Takeshi Tanaka ,  Masami Inoue ,  Martin John McCaslin

Inventor： Voonyee Ho ,  Takeshi Tanaka ,  Masami Inoue ,  Martin John McCaslin

IPC: H05K1/09

CPC classification number: H05K1/0271 ,  G11B5/486 ,  H05K1/0237 ,  H05K1/028 ,  H05K1/167 ,  H05K3/244 ,  H05K2201/0352 ,  H05K2201/09236 ,  H05K2201/09672 ,  Y10T29/49124

Abstract: A first insulating layer is formed on a suspension body. A write wiring trace is formed on the first insulating layer. A second insulating layer is formed on the first insulating layer to cover the write wiring trace. A write wiring trace and read wiring traces are formed on the second insulating layer. The write wiring trace is arranged above the write wiring trace. The write wiring trace includes a conductor layer and reinforcing alloy layers. The reinforcing alloy layers are sequentially formed to cover an upper surface and side surfaces of the conductor layer.

Abstract translation: 在悬架体上形成第一绝缘层。 在第一绝缘层上形成写入布线。 在第一绝缘层上形成第二绝缘层以覆盖写入布线迹线。 写入布线迹线和读取布线迹线形成在第二绝缘层上。 写入布线迹线布置在写入布线迹线的上方。 写入布线迹线包括导体层和增强合金层。 依次形成加强合金层以覆盖导体层的上表面和侧表面。

公开(公告)号：US20120331429A1

公开(公告)日：2012-12-27

申请号：US13603732

申请日：2012-09-05

Applicant: Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

Inventor： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/0253 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49117 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24322

Abstract: Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

Abstract translation: 具有带状段互连的通孔上的参考平面空隙的制造电路允许在通孔上路由关键信号路径，同时仅通过插入电容略微增加。 传输线参考平面定义了通过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会被阻抗失配降级，否则会由分流电容引起 信号承载PTH的顶部（或底部）到传输线参考平面。 为了提供增加的布线密度，信号路径被布置在空隙上，但是通过将导电条包括通过空隙来防止由空隙引起的信号路径的破坏，从而减小与信号承载PTH的耦合并维持 信号路径导体。

公开(公告)号：US20120329326A1

公开(公告)日：2012-12-27

申请号：US13606420

申请日：2012-09-07

Applicant: Jack E. Caveney ,  Masud Bolouri-Saransar

Inventor： Jack E. Caveney ,  Masud Bolouri-Saransar

IPC: H01R13/719

CPC classification number: H01R13/6461 ,  H01R13/6464 ,  H01R13/6466 ,  H01R13/66 ,  H01R13/6658 ,  H01R24/64 ,  H05K1/0228 ,  H05K1/162 ,  H05K2201/09672 ,  H05K2201/10189 ,  Y10S439/941

Abstract: A communication jack having crosstalk compensation features for overall crosstalk interference reduction is disclosed. In one embodiment, the jack is configured to receive a plug to form a communication connection, and comprises jack contacts disposed in the jack, with each contact having at least a first surface and a second surface. Upon the plug being received by the jack, the plug contacts interface with the first surface of the jack contacts. The jack further includes a first capacitive coupling connected between two pairs of jack contacts to compensate for near end crosstalk, with the first capacitive coupling being connected to the pairs of jack contacts along the second surface adjacent to where the plug contacts interface with the jack contacts. A far end crosstalk compensation scheme is also set forth.

Abstract translation: 公开了一种具有用于整个串扰干扰减少的串扰补偿特征的通信插座。 在一个实施例中，千斤顶配置成接收插头以形成通信连接，并且包括设置在插座中的插座触点，每个触头具有至少第一表面和第二表面。 当插头被插座接收时，插头触点与插座触点的第一表面接触。 插座还包括连接在两对插座触点之间的第一电容耦合器，以补偿近端串扰，第一电容耦合器沿着与插座触头与插座触头相接触的第二表面连接到插座触点对 。 还提出了远端串扰补偿方案。

公开(公告)号：US08310645B2

公开(公告)日：2012-11-13

申请号：US12995578

申请日：2009-04-10

Applicant: Takashi Matsui ,  Motoji Shiota

Inventor： Takashi Matsui ,  Motoji Shiota

IPC: G02F1/1343 ,  G02F1/1345

CPC classification number: H05K1/111 ,  G02F1/13452 ,  H01L2224/05553 ,  H05K2201/09409 ,  H05K2201/09672 ,  H05K2201/10674 ,  Y02P70/611

Abstract: A wiring board of the present invention has pads disposed in a plurality of rows including: first row pads each being connected to a respective one of the connection wires that is long in length; and second row pads (30b) each being connected to a respective one of the connection wires that is shorter in length than that of first connection wires (10a) connected to the first row pads, each of the first connection wires (10a) being provided not in a region between adjacent ones of the second row pads (30b) but in a lower layer region of the second row pads (30b), in such a manner that at least a first insulating layer (20a) is sandwiched between the second row pads (30b) and the first connection wires (10a), and 0.8≦W1/W2≦1, where W1 is a line width of the first connection wires (10a) in the lower layer region of the second row pads (30b), and W2 is a width of the second row pads (30b).

Abstract translation: 本发明的布线基板具有排列成多行的焊盘，包括：第一行焊盘，各自连接到长度相等的连接线; 和第二排焊盘（30b）分别连接到长度比连接到第一行焊盘的第一连接线（10a）短的连接线中的每个连接线，每个第一连接线（10a）被设置 不是在相邻的第二列焊盘（30b）之间的区域中，而是在第二行焊盘（30b）的下层区域中，使得至少第一绝缘层（20a）夹在第二行 焊盘（30b）和第一连接线（10a），以及0.8＆lt; W1; W1 / W2＆nlE; 1，其中W1是第二行焊盘（30b）的下层区域中的第一连接线（10a）的线宽， ，W2是第二排焊盘（30b）的宽度。