公开(公告)号：US07262368B2

公开(公告)日：2007-08-28

申请号：US10917978

申请日：2004-08-13

Applicant: Belgacem Haba ,  Masud Beroz ,  David B. Tuckerman ,  Giles Humpston ,  Richard Dewitt Crisp

Inventor： Belgacem Haba ,  Masud Beroz ,  David B. Tuckerman ,  Giles Humpston ,  Richard Dewitt Crisp

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H01L23/49838 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/041 ,  H05K3/06 ,  H05K3/202 ,  H05K3/4038 ,  H05K2201/09609 ,  H05K2201/097 ,  H05K2201/09827 ,  H05K2201/09881 ,  H05K2203/0733 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49165 ,  H01L2924/00

Abstract: Provided are connection structures for a microelectronic device and methods for forming the structure. A substrate is included having opposing surfaces and a plurality of holes extending through the surfaces. Also included is a plurality of electrically conductive posts. Each post extends from a base to a tip located within a corresponding hole of the substrate. An additional substrate may be provided such that the base of each post is located on a surface thereof. Additional electrically conductive posts may be provided having tips in corresponding holes of the additional substrate. Optionally, a dielectric material may be placed between the substrate and the posts.

Abstract translation: 提供了用于微电子器件的连接结构和用于形成结构的方法。 包括具有相对表面的基板和延伸穿过该表面的多个孔。 还包括多个导电柱。 每个柱从基部延伸到位于基板的相应孔内的尖端。 可以提供另外的基底，使得每个柱的基部位于其表面上。 可以提供额外的导电柱，其具有在附加衬底的相应孔中的尖端。 可选地，介电材料可以放置在基板和柱之间。

公开(公告)号：US07244647B2

公开(公告)日：2007-07-17

申请号：US11264999

申请日：2005-11-01

Applicant: Ruei-Chih Chang

Inventor： Ruei-Chih Chang

IPC: H01L21/8242

CPC classification number: H01L23/49822 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K1/162 ,  H05K3/4644 ,  H05K2201/0209 ,  H05K2201/09672 ,  H05K2201/09881 ,  Y10T29/417 ,  Y10T29/435 ,  H01L2924/00

Abstract: An embedded capacitor structure in a circuit board and a method for fabricating the same are proposed. The circuit board is formed with a first circuit layer on at least one surface thereof, wherein the first circuit layer has at least one first electrode plate for the capacitor structure. Then, a dielectric layer is formed on the first circuit layer and made flush with the first circuit layer. The dielectric layer has a relatively low dielectric constant and good fluidity to effectively fill the spaces between patterned traces of the first circuit later. A capacitive material is deposited on the dielectric layer and the first circuit layer. Finally, a second circuit layer is formed on the capacitive material and has at least one second electrode plate corresponding to the first electrode plate, together with the capacitive material disposed in-between, to form the capacitor structure.

Abstract translation: 提出了一种电路板中的嵌入式电容器结构及其制造方法。 电路板在其至少一个表面上形成有第一电路层，其中第一电路层具有用于电容器结构的至少一个第一电极板。 然后，在第一电路层上形成电介质层并与第一电路层齐平。 介电层具有相对低的介电常数和良好的流动性，以有效地填充第一电路的图案化迹线之后的空间。 在电介质层和第一电路层上沉积电容材料。 最后，在电容材料上形成第二电路层，并且具有至少一个对应于第一电极板的第二电极板以及设置在其间的电容材料，以形成电容器结构。

公开(公告)号：US20070128855A1

公开(公告)日：2007-06-07

申请号：US11634970

申请日：2006-12-07

Applicant: Hye Cho ,  Jae Joung ,  Sung Oh

Inventor： Hye Cho ,  Jae Joung ,  Sung Oh

IPC: H01L21/4763

CPC classification number: H05K3/4664 ,  H05K3/125 ,  H05K3/4647 ,  H05K2201/0154 ,  H05K2201/09881 ,  H05K2203/013

Abstract: Provided is a method for manufacturing a printed wiring board, which can enhance the peel strength between an insulating layer and a conductive pattern by a two-step process, that is, a semi-hardening and full-hardening of the insulating layer. In the method for manufacturing the printed wiring board having one or more layers of a conductive pattern and an insulating pattern, an insulating pattern is formed on an insulating substrate, and at least one of the insulating substrate and the insulating pattern is semi-hardened. A conductive pattern is formed on the insulating substrate and/or the insulating pattern, thereby providing a stack structure. Then, a thermal treatment is performed on the stack structure to fully harden the semi-hardened insulating substrate and/or insulating pattern, and the conductive pattern is fired.

Abstract translation: 提供一种印刷电路板的制造方法，其可以通过两步法（即，绝缘层的半硬化和全硬化）来提高绝缘层和导电图案之间的剥离强度。 在制造具有一层或多层导电图案和绝缘图案的印刷线路板的方法中，在绝缘基板上形成绝缘图案，绝缘基板和绝缘图案中的至少一个被半硬化。 在绝缘基板和/或绝缘图案上形成导电图案，从而提供堆叠结构。 然后，对堆叠结构进行热处理，以使半硬化绝缘基板和/或绝缘图案完全硬化，并且导电图案被烧制。

公开(公告)号：US20060099728A1

公开(公告)日：2006-05-11

申请号：US11304558

申请日：2005-12-16

Applicant: Bily Wang ,  Jonnie Chuang ,  Hui-Yen Huang

Inventor： Bily Wang ,  Jonnie Chuang ,  Hui-Yen Huang

IPC: H01L21/00

CPC classification number: H05K3/0052 ,  H05K1/056 ,  H05K3/445 ,  H05K2201/09881 ,  H05K2203/0228 ,  H05K2203/0278 ,  H05K2203/1536

Abstract: A method of manufacturing a substrate structure includes the steps of: (1) providing a metal substrate having a metal portion; (2) chemically etching a plurality of trenches in the metal substrate; (3) applying a polymer composite material into the trenches to form a substrate having a polymer composite portion abutted to the metal portion; (4) polishing a surface of the substrate to make a height of the polymer composite portion equal to that of the metal portion; (5) forming a covering material on the surface of the substrate; and (6) cutting the substrate via the polymer composite portion for decreasing cutting bur produced on the metal portion. Furthermore, the method is provided for combining the metal substrate and the polymer composite material, thereby to increase cutting precision and strength of the substrate structure.

Abstract translation: 一种制造衬底结构的方法包括以下步骤：（1）提供具有金属部分的金属衬底; （2）化学蚀刻金属基板中的多个沟槽; （3）将聚合物复合材料施加到沟槽中以形成具有与金属部分邻接的聚合物复合部分的基底; （4）研磨基板的表面，使聚合物复合部的高度与金属部的高度相等; （5）在基板的表面上形成覆盖材料; 和（6）通过聚合物复合部分切割基底以减少在金属部分上产生的切割毛刺。 此外，提供了用于组合金属基板和聚合物复合材料的方法，从而提高基板结构的切割精度和强度。

公开(公告)号：US20060038303A1

公开(公告)日：2006-02-23

申请号：US10924396

申请日：2004-08-23

Applicant: Terry Sterrett ,  Devendra Natekar

Inventor： Terry Sterrett ,  Devendra Natekar

IPC: H01L23/48

CPC classification number: H05K3/4038 ,  H01L21/486 ,  H01L23/49827 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/14 ,  H05K3/06 ,  H05K2201/09881 ,  H05K2201/10378 ,  H05K2201/2018 ,  H05K2203/0369 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In one embodiment, a package-to-package stack is assembled comprising a first integrated circuit package, and a second integrated circuit package which are mechanically and electrically connected using an interposer. In one embodiment, the interposer 106 includes columnar interconnects which may be fabricated by etching a conductive member such as copper foil, for example. In one application, the pitch or center to center spacing of the columnar interconnects may be defined by masking techniques to provide an interconnect pitch suitable for a particular application. In yet another aspect, etching rates may be controlled to provide height to width aspect ratios of the columnar interconnects which are suitable for various applications.

公开(公告)号：US20060035406A1

公开(公告)日：2006-02-16

申请号：US10918371

申请日：2004-08-16

Applicant: Bily Wang ,  Jonnie Chuang ,  Hui-Yen Huang

Inventor： Bily Wang ,  Jonnie Chuang ,  Hui-Yen Huang

IPC: H01L21/50 ,  H01L23/48

CPC classification number: H05K3/445 ,  H05K1/056 ,  H05K3/0052 ,  H05K2201/09881 ,  H05K2203/0228 ,  H05K2203/0278 ,  H05K2203/1536

Abstract: A semiconductor substrate structure includes a substrate having a trench formed thereon, a polymer composite material supplied into the trench and an electroplate conductive layer formed on the substrate. Further, a semiconductor substrate processing method includes the steps of: providing a substrate forming a trench thereon, supplying a polymer composite material into the trench, polishing a surface of the substrate and forming a covering material on the surface of the substrate. Therefore, the method is provided for combining the polymer composite material into the substrate, thereby to raise cutting precision and strength of the semiconductor substrate structure.

Abstract translation: 半导体衬底结构包括其上形成有沟槽的衬底，提供到沟槽中的聚合物复合材料和形成在衬底上的电镀导电层。 此外，半导体衬底处理方法包括以下步骤：提供在其上形成沟槽的衬底，将聚合物复合材料供应到沟槽中，抛光衬底的表面并在衬底的表面上形成覆盖材料。 因此，提供了将聚合物复合材料组合到基板中的方法，从而提高半导体基板结构的切割精度和强度。

公开(公告)号：US20060035072A1

公开(公告)日：2006-02-16

申请号：US11200184

申请日：2005-08-10

Applicant: Kyotaro Abe ,  Tamotsu Ishiyama ,  Shigeki Sato

Inventor： Kyotaro Abe ,  Tamotsu Ishiyama ,  Shigeki Sato

IPC: C03B29/00 ,  B32B18/00

CPC classification number: C04B35/6342 ,  C04B35/4682 ,  C04B35/6261 ,  C04B35/62625 ,  C04B35/6263 ,  C04B35/6264 ,  C04B35/62665 ,  C04B35/632 ,  C04B35/64 ,  C04B2235/3206 ,  C04B2235/3215 ,  C04B2235/3225 ,  C04B2235/3239 ,  C04B2235/3262 ,  C04B2235/3436 ,  C04B2235/3454 ,  C04B2235/5445 ,  C04B2235/6025 ,  C04B2235/6582 ,  C04B2235/663 ,  H01G4/308 ,  H05K1/0306 ,  H05K3/207 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/09881 ,  H05K2203/0156 ,  Y10T428/252

Abstract: A release layer paste used for producing a multilayer electronic device, used in combination with an electrode layer paste including terpineol, dehydroterpineol, terpineol acetate, or dehydroterpineol acetate and including a ceramic powder, organic vehicle, plasticizer, and dispersion agent, the organic vehicle containing a binder having polyvinyl acetal as its main ingredient, a ratio (P/B) of the ceramic powder and the binder and plasticizer being controlled to 1.33 to 5.56 (however, excluding 5.56).

公开(公告)号：US20060013970A1

公开(公告)日：2006-01-19

申请号：US11146136

申请日：2005-06-07

Applicant: Kenji Wada

Inventor： Kenji Wada

IPC: B05D5/12 ,  B41M5/00

CPC classification number: H05K3/4664 ,  H05K3/125 ,  H05K3/28 ,  H05K2201/09881 ,  H05K2203/013

Abstract: A method for providing a layer by ink jetting, comprising: (a) discharging a first liquid insulating material of a first concentration on a surface of a first level so that a side of a first conductive layer placed on the surface is covered by the first insulating material; (b) providing a first insulating layer facing the first conductive layer by one of activating and drying the first insulating material that has been discharged; (c) discharging a second liquid insulating material of a second concentration on the first conductive layer and the first insulating layer, the second concentration being higher than the first concentration; and (d) providing a second insulating layer covering the first conductive layer and the first insulating layer by one of activating and drying the second insulating material that has been discharged.

Abstract translation: 一种通过喷墨提供层的方法，包括：（a）在第一层的表面上排出第一浓度的第一液体绝缘材料，使得放置在表面上的第一导电层的一侧被第一层 绝缘材料; （b）通过激活和干燥已经排出的第一绝缘材料之一来提供面向第一导电层的第一绝缘层; （c）在第一导电层和第一绝缘层上排出第二浓度的第二液体绝缘材料，第二浓度高于第一浓度; 和（d）通过激活和干燥已经排出的第二绝缘材料之一来提供覆盖第一导电层和第一绝缘层的第二绝缘层。

公开(公告)号：US20060005994A1

公开(公告)日：2006-01-12

申请号：US11156586

申请日：2005-06-21

Applicant: Hideo Imai ,  Kazuaki Sakurada

Inventor： Hideo Imai ,  Kazuaki Sakurada

IPC: H05K1/00

CPC classification number: H05K3/4664 ,  H05K1/0393 ,  H05K3/108 ,  H05K3/125 ,  H05K3/184 ,  H05K3/4685 ,  H05K2201/09881 ,  H05K2203/013 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: A method of manufacturing a wiring board includes steps of: providing a substrate; forming a first wiring layer on the substrate by photolithography; forming a first insulating layer by ink jetting so as to cover a part of the first wiring layer and expose an exposed section of the first wiring layer; and forming a second wiring layer by ink jetting partly over the first wiring layer, with the first insulating layer being between the part of the first wiring layer and a part of the second wiring layer. A wider variety of conductive material and insulating material can be used for forming the wiring layers and the insulating layers on the substrate by ink jetting, while the wiring board has a first wiring layer having high density.

Abstract translation: 制造布线板的方法包括以下步骤：提供基板; 通过光刻在基板上形成第一布线层; 通过喷墨形成第一绝缘层，以覆盖第一布线层的一部分并暴露第一布线层的暴露部分; 以及通过部分地在所述第一布线层上的喷墨形成第二布线层，所述第一绝缘层位于所述第一布线层的所述部分和所述第二布线层的一部分之间。 可以使用更多种导电材料和绝缘材料来通过喷墨形成布线层和基板上的绝缘层，同时布线板具有高密度的第一布线层。

公开(公告)号：US20050266608A1

公开(公告)日：2005-12-01

申请号：US10945961

申请日：2004-09-22

Applicant: Kwun-Yao Ho ,  Moriss Kung

Inventor： Kwun-Yao Ho ,  Moriss Kung

IPC: H01L21/48 ,  H01L23/538 ,  H05K3/24 ,  H05K3/28 ,  H05K3/34 ,  H05K3/42

CPC classification number: H01L21/4846 ,  H01L21/486 ,  H05K3/242 ,  H05K3/243 ,  H05K3/28 ,  H05K3/282 ,  H05K3/3457 ,  H05K3/42 ,  H05K2201/0195 ,  H05K2201/09881 ,  H05K2203/054 ,  H05K2203/1581 ,  Y10T29/49124

Abstract: A packaging substrate without plating bar and a method of forming the same is provided. A substrate is firstly provided with circuit patterns formed thereon. Then, solder masks are formed to define connecting points on the circuit patterns. Afterward, the openings of the solder mask on a bottom surface of the substrate are filled with solder material. Thereafter, a seed layer is formed on the bottom surface of the solder mask and the solder material, and then a passivation layer is formed on a surface of the seed layer. Finally, a plating process is carried out by using the seed layer to input cathode electric level to form metal pads on the defined connecting points on the upper surface of the substrate.

Abstract translation: 提供一种不含电镀条的包装基材及其形成方法。 首先在其上形成有电路图案的基板。 然后，形成焊接掩模以限定电路图案上的连接点。 之后，衬底的底面上的焊料掩模的开口被焊料材料填充。 此后，在焊料掩模和焊料材料的底表面上形成种子层，然后在种子层的表面上形成钝化层。 最后，通过使用种子层来进行电镀处理，以输入阴极电平，以在衬底的上表面上限定的连接点上形成金属焊盘。