公开(公告)号：US20140111946A1

公开(公告)日：2014-04-24

申请号：US14143465

申请日：2013-12-30

Applicant: ABB AG

Inventor： Stefan GUTERMUTH

IPC: H05K1/02

CPC classification number: H05K1/021 ,  H05K1/0201 ,  H05K1/0203 ,  H05K2201/062 ,  H05K2201/09063 ,  H05K2201/09972

Abstract: An arrangement for cooling subassemblies of an automation or control system is disclosed, wherein the subassemblies each comprise at least one printed circuit board (LP) having electronic components of different temperature sensitivity arranged thereon. The printed circuit board (LP) has at least one first portion for temperature-sensitive components and at least one second portion for temperature-insensitive components that generate waste heat. Interspaces are arranged between the first portion and the second portion, the interspaces each forming a thermally insulated trench. Means can be provided which keep away the heat over the temperature-sensitive components in a suitable manner and dissipate the waste heat from the printed circuit board (LP) before the heat reaches the temperature-sensitive components.

Abstract translation: 公开了一种用于冷却自动化或控制系统的子组件的装置，其中每个子组件包括至少一个布置有不同温度敏感度的电子部件的印刷电路板（LP）。 印刷电路板（LP）具有用于温度敏感部件的至少一个第一部分和用于产生废热的不敏感温度部件的至少一个第二部分。 间隙布置在第一部分和第二部分之间，间隙各自形成绝热沟槽。 可以提供能够以合适的方式将热量超过温度敏感部件的装置，并且在热到达温度敏感部件之前散发来自印刷电路板（LP）的废热。

公开(公告)号：US08704106B2

公开(公告)日：2014-04-22

申请号：US13113229

申请日：2011-05-23

Applicant: Masataka Mizukoshi ,  Yoshikatsu Ishizuki

Inventor： Masataka Mizukoshi ,  Yoshikatsu Ishizuki

IPC: H05K1/11

CPC classification number: H05K3/20 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/10175 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81001 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/83193 ,  H01L2224/838 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/1517 ,  H01L2924/15788 ,  H01L2924/1579 ,  H05K1/142 ,  H05K3/4658 ,  H05K3/4694 ,  H05K2201/0108 ,  H05K2201/0352 ,  H05K2201/09972 ,  H05K2203/025 ,  H05K2203/1189 ,  Y10T29/49117 ,  Y10T156/1052 ,  Y10T428/24917 ,  H01L2924/00 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2224/16225

Abstract: A method of manufacturing an electronic component includes forming a resin layer over an underlying layer, pressing a conductor plate including a pattern formed on one major surface thereof against the resin layer, and embedding the pattern in the resin layer, and performing polishing, Chemical Mechanical Polishing, or cutting by the use of a diamond bit on another major surface of the conductor plate until the resin layer appears, and leaving the pattern in the resin layer as a conductor pattern.

Abstract translation: 电子部件的制造方法包括在下层上形成树脂层，将包含形成在其一个主表面上的图案的导体板压在树脂层上，将图案嵌入树脂层中，进行抛光，化学机械 通过在导体板的另一个主表面上使用金刚石钻头进行抛光或切割，直到出现树脂层，并将图案留在树脂层中作为导体图案。

公开(公告)号：US08702998B1

公开(公告)日：2014-04-22

申请号：US13416992

申请日：2012-03-09

Applicant: Albert J. Guerini

Inventor： Albert J. Guerini

IPC: H01B13/00

CPC classification number: H05K3/188 ,  G11B5/4846 ,  H05K3/06 ,  H05K2201/09236 ,  H05K2201/09972 ,  H05K2203/0716 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49153 ,  Y10T29/49155

Abstract: A novel method to manufacture a flexible cable for a disk drive is disclosed. The method includes providing a flexible laminar sheet. The flexible laminar sheet has a dielectric substrate layer and an electrically conductive layer contacting a first side of the dielectric substrate layer. A portion of the electrically conductive layer is etched away to define a first plurality of electrically conductive traces and to expose an etched surface of the first side of the dielectric substrate layer. A second plurality of electrically conductive traces is deposited on the etched surface of the first side of the dielectric substrate layer.

Abstract translation: 公开了一种用于制造用于磁盘驱动器的柔性电缆的新方法。 该方法包括提供柔性层流片。 柔性层状片具有电介质基底层和与电介质基底层的第一面接触的导电层。 蚀刻导电层的一部分以限定第一多个导电迹线并暴露电介质基底层的第一侧的蚀刻表面。 第二多个导电迹线沉积在电介质基底层的第一侧的蚀刻表面上。

公开(公告)号：US20140098505A1

公开(公告)日：2014-04-10

申请号：US13646610

申请日：2012-10-05

Applicant: APPLE INC.

Inventor： John J. Baker

IPC: H05K1/18 ,  H05K3/30

CPC classification number: H05K3/284 ,  H05K3/28 ,  H05K2201/09972 ,  H05K2201/10189 ,  H05K2201/10356 ,  H05K2201/10446 ,  H05K2203/1327 ,  H05K2203/1476 ,  Y10T29/49146

Abstract: An improved method for producing a PCB assembly requiring at least two different encapsulants is disclosed. The PCB assembly may have two or more separate regions in which electronic devices are attached. In each region, a unique encapsulant with different mechanical, electrical, physical and or chemical properties is used according to the particular requirements of the electronic devices in that region.

Abstract translation: 公开了一种用于生产需要至少两种不同密封剂的PCB组件的改进方法。 PCB组件可以具有两个或更多个独立的区域，其中电子设备被附接。 在每个区域中，根据该区域的电子设备的特殊要求，使用具有不同机械，电学，物理和/或化学性质的独特的密封剂。

公开(公告)号：US08685796B2

公开(公告)日：2014-04-01

申请号：US11856730

申请日：2007-09-18

Applicant: Yoichiro Kurita ,  Koji Soejima ,  Masaya Kawano

Inventor： Yoichiro Kurita ,  Koji Soejima ,  Masaya Kawano

IPC: H01L21/44

CPC classification number: H01L23/3128 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/3135 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/18 ,  H01L2221/68345 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K3/0058 ,  H05K3/284 ,  H05K3/4682 ,  H05K2201/0195 ,  H05K2201/09527 ,  H05K2201/09972 ,  H05K2203/016 ,  H05K2203/1469 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: The electronic device includes a first interconnect layer and a second interconnect layer. The second interconnect layer is provided on the lower surface of the first interconnect layer. The first interconnect layer includes a via plug (first conductive plug). An end face of the via plug on the side of the second interconnect layer is smaller in area than the opposite end face. The via plug is exposed on the surface of the first interconnect layer facing the second interconnect layer. An insulating resin forming the first interconnect layer is higher in thermal decomposition temperature than an insulating resin forming the second interconnect layer.

Abstract translation: 电子设备包括第一互连层和第二互连层。 第二互连层设置在第一互连层的下表面上。 第一互连层包括通孔插头（第一导电插头）。 通孔塞在第二互连层一侧的端面的面积小于相对端面。 通孔插头暴露在面向第二互连层的第一互连层的表面上。 形成第一互连层的绝缘树脂的热分解温度高于形成第二互连层的绝缘树脂。

公开(公告)号：US08669758B2

公开(公告)日：2014-03-11

申请号：US13949031

申请日：2013-07-23

Applicant: Broadcom Corporation

Inventor： Iain Barnett ,  William Michael James Holland ,  Jonathan Ephraim David Hurwitz

IPC: G01R19/00

CPC classification number: H05K1/162 ,  G01R15/06 ,  G01R15/16 ,  G01R19/12 ,  G01R19/175 ,  H03H7/004 ,  H05K1/0239 ,  H05K1/0256 ,  H05K2201/09309 ,  H05K2201/09972

Abstract: A voltage measurement circuit is operative to measure a high voltage AC signal and includes a capacitive divider circuit and a compensator circuit. The capacitive divider circuit includes first and second inputs, across which, in use, is received a high voltage AC signal and also includes second and third capacitors. First and second plates of each of the first, second and third capacitors are defined by conductive layers of a printed circuit board and the dielectric of each of the first, second and third capacitors being defined by a non-conducting part of the printed circuit board. A compensator circuit has a configurable transfer function and includes an input connected across the first and second plates of the third capacitor and an output. The compensator circuit is operative to change a voltage received at its input in accordance with the transfer function and to provide the changed voltage at its output.

Abstract translation: 电压测量电路用于测量高压AC信号，并包括电容分压器电路和补偿电路。 电容分压器电路包括第一和第二输入，在使用中，它们被接收高压AC信号，并且还包括第二和第三电容器。 第一，第二和第三电容器中的每一个的第一和第二板由印刷电路板的导电层限定，并且第一，第二和第三电容器中的每一个的电介质由印刷电路板的非导电部分限定 。 补偿电路具有可配置的传递函数，并且包括连接在第三电容器的第一和第二板上的输入端和输出端。 补偿电路可操作以根据传递函数改变其输入处接收的电压，并在其输出端提供改变的电压。

公开(公告)号：US08633395B2

公开(公告)日：2014-01-21

申请号：US12995514

申请日：2009-05-22

Applicant: Tadahiro Ohmi ,  Shigetoshi Sugawa ,  Hiroshi Imai ,  Akinobu Teramoto

Inventor： Tadahiro Ohmi ,  Shigetoshi Sugawa ,  Hiroshi Imai ,  Akinobu Teramoto

IPC: H05K1/03 ,  H05K1/11

CPC classification number: H05K1/0218 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6688 ,  H01L2924/0002 ,  H01L2924/19032 ,  H01L2924/3011 ,  H05K1/025 ,  H05K1/0265 ,  H05K3/4652 ,  H05K2201/0191 ,  H05K2201/0352 ,  H05K2201/0715 ,  H05K2201/096 ,  H05K2201/09618 ,  H05K2201/09727 ,  H05K2201/09972 ,  H01L2924/00

Abstract: A multilayer wiring board 100 comprises a first wiring region 101 where wirings 103a and insulating layers 104a and 104b are alternately laminated, and a second wiring region 102 where a thickness H2 of an insulating layer 104 is twice or more a thickness H1 of the insulating layer in the first wiring region 101 and a width W2 of a wiring 103b is twice or more a width W1 of the wiring in the first wiring region 101. The first wiring region 101 and the second wiring region 102 are integrally formed on the same board.

Abstract translation: 多层布线基板100包括：布线103a和绝缘层104a，104b交替层叠的第一布线区域101和绝缘层104的厚度H2为绝缘层的厚度H1的两倍以上的第二布线区域102 在第一布线区域101中，布线103b的宽度W2是第一布线区域101中的布线的宽度W1的两倍或更多倍。第一布线区域101和第二布线区域102一体地形成在同一个板上。

公开(公告)号：US08553470B2

公开(公告)日：2013-10-08

申请号：US13047602

申请日：2011-03-14

Applicant: Terry R. Lee ,  Joseph M. Jeddeloh

Inventor： Terry R. Lee ,  Joseph M. Jeddeloh

IPC: G11C7/10

CPC classification number: G11C5/02 ,  H05K1/0298 ,  H05K1/181 ,  H05K2201/09972 ,  Y02P70/611

Abstract: A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time. In an alternate embodiment, the printed circuit board includes a driver sector electrically isolated from the other sectors and having a multi-layer structure, the driver being attached to the driver sector.

公开(公告)号：US20130221811A1

公开(公告)日：2013-08-29

申请号：US13771837

申请日：2013-02-20

Applicant: JTEKT CORPORATION

Inventor： Nobuhiro UCHIDA

IPC: H02K11/00

CPC classification number: H02K11/0073 ,  B62D5/0406 ,  H02K11/33 ,  H05K1/0203 ,  H05K1/0298 ,  H05K3/0061 ,  H05K5/0043 ,  H05K2201/09972 ,  H05K2201/0999

Abstract: In a circuit board, a control pattern portion in which control circuit patterns are formed and a drive pattern portion in which drive circuit patterns are formed are formed in different regions. A recessed portion is formed in a base, and the drive pattern portion is fixed to the base such that insulation between a drive circuit and the base is maintained and the control pattern portion is arranged above the recessed portion. In this way, a space in which a circuit element is able to be mounted is formed between the control pattern portion and the recessed portion.

Abstract translation: 在电路板中，形成有控制电路图案的控制图形部分和形成有驱动电路图案的驱动图案部分形成在不同的区域中。 在基座上形成有凹部，驱动图形部固定在基座上，使驱动电路和基座之间的绝缘保持，并且控制图形部分配置在凹部的上方。 以这种方式，在控制图案部分和凹陷部分之间形成有能够安装电路元件的空间。

公开(公告)号：US20130206443A1

公开(公告)日：2013-08-15

申请号：US13879456

申请日：2011-10-20

Applicant: Manabu Ooishi ,  Maki Sugiura ,  Kazuhiro Yamamoto

Inventor： Manabu Ooishi ,  Maki Sugiura ,  Kazuhiro Yamamoto

IPC: H02G5/00 ,  H05K5/04

CPC classification number: H02G5/005 ,  H05K1/0271 ,  H05K1/056 ,  H05K5/04 ,  H05K2201/09972

Abstract: The electrical junction box is provided with a metal core substrate including: a rectangular-shaped core metal layer in which two core metal plates are arranged with a slit-shaped gap therebetween; and insulating layers filling the gap and integrating the two core metal plates by covering surfaces of the core metal plates. Electric power from a battery is inputted into the core metal plate, and electric power from an alternator is inputted into the core metal plate. The gap includes: a first straight portion vertically extended straight from one side of the core metal layer; a second straight portion vertically extended straight from another side of the core metal layer, parallel to a virtual extended line of the first straight portion, and not arranged in the same line as the first straight portion; and a square-U-shaped portion.

Abstract translation: 电接线盒设置有金属芯基板，该金属芯基板包括矩形的芯金属层，两芯芯金属板之间形成有狭缝间隙， 以及填充间隙的绝缘层，并且通过覆盖芯金属板的表面来整合两个芯金属板。 来自电池的电力被输入到芯金属板中，并且来自交流发电机的电力被输入到芯金属板中。 间隙包括：从芯金属层的一侧直线垂直延伸的第一直线部分; 从芯金属层的另一侧向下垂直延伸的第二直线部分，平行于第一直线部分的虚拟延伸线，并且不与第一直线部分布置在同一条线上; 和一个正方形的U形部分。