公开(公告)号：US12072833B2

公开(公告)日：2024-08-27

申请号：US17852264

申请日：2022-06-28

Applicant: Imagination Technologies Limited

Inventor： Bert Hindle ,  Ben Fletcher

IPC: G06F9/44 ,  G05B19/04 ,  G05B19/045 ,  G06F9/4401 ,  G06F13/12 ,  G06F15/17 ,  G06F15/177 ,  G06F15/78 ,  G06F1/32

CPC classification number: G06F15/177 ,  G05B19/04 ,  G05B19/045 ,  G06F9/44 ,  G06F9/4411 ,  G06F13/12 ,  G06F13/124 ,  G06F15/17 ,  G06F15/78 ,  G06F15/7821 ,  G06F1/32 ,  Y02D10/00

Abstract: An integrated circuit includes a memory configured to store a plurality of functions; a mapping interface configured to perform a mapping from a received first signal to a first function of the plurality of functions; and a state machine configured to, in response to said mapping, execute the first function; wherein the integrated circuit is arranged to, in dependence on the execution of the first function at the state machine, modify said mapping between the first signal and the first function so as to re-map the first signal to a second function of the plurality of functions such that, on receiving a subsequent first signal, the state machine is configured to execute the second function.

公开(公告)号：US20240273805A1

公开(公告)日：2024-08-15

申请号：US18642375

申请日：2024-04-22

Applicant: Imagination Technologies Limited

Inventor： Rostam King ,  William Thomas

IPC: G06T15/00 ,  G06T15/04

CPC classification number: G06T15/005 ,  G06T15/04

Abstract: A method of operation of a texturing/shading unit in a GPU pipeline is used for efficient convolution operations. The method uses texture hardware to collectively fetch all the texels required to calculate properties for a group of output pixels without any duplication. The method then bypasses bilinear filter hardware in the texture hardware and passes the fetched and unfiltered texel data from the texture hardware unit to shader hardware in the texturing/shading unit. The shader hardware uses the fetched texel data to perform a plurality of convolution operations to calculate the properties of each of the output pixel.

公开(公告)号：US20240273669A1

公开(公告)日：2024-08-15

申请号：US18394274

申请日：2023-12-22

Applicant: Imagination Technologies Limited

Inventor： Aroun Demeure ,  William Thomas ,  Alexander Hoffmann ,  Arturo Barrabes

IPC: G06T1/60 ,  G06T1/20 ,  G06T11/00

CPC classification number: G06T1/60 ,  G06T1/20 ,  G06T11/001

Abstract: A method and graphics processing unit (GPU) are provided for applying texture processing to a block of fragments, each of the fragments being associated with a texture coordinate for each of a plurality of dimensions of a texture. A fragment processing unit of the GPU detects that the texture coordinates for the fragments of the block are axis-aligned, and in response to detecting that the texture coordinates for the fragments of the block are axis-aligned, sends a reduced set of texture coordinates to a texture processing unit of the GPU. The texture processing unit: (i) processes the reduced set of texture coordinates to generate texel addresses of texels to be fetched, (ii) fetches texels using the generated texel addresses, (iii) determines a processed value for each of the fragments of the block based on the fetched texels, and (iv) outputs the processed values.

公开(公告)号：US12051159B2

公开(公告)日：2024-07-30

申请号：US18205121

申请日：2023-06-02

Applicant: Imagination Technologies Limited

Inventor： Simon Fenney

IPC: G06T17/20 ,  G06T9/00 ,  G06T15/00

CPC classification number: G06T17/20 ,  G06T9/00 ,  G06T15/005

Abstract: A method and apparatus for rendering a computer-generated image using a stencil buffer is described. The method divides an arbitrary closed polygonal contour into first and higher level primitives, where first level primitives correspond to contiguous vertices in the arbitrary closed polygonal contour and higher level primitives correspond to the end vertices of consecutive primitives of the immediately preceding primitive level. The method reduces the level of overdraw when rendering the arbitrary polygonal contour using a stencil buffer compared to other image space methods. A method of producing the primitives in an interleaved order, with second and higher level primitives being produced before the final first level primitives of the contour, is described which improves cache hit rate by reusing more vertices between primitives as they are produced.

公开(公告)号：US20240248750A1

公开(公告)日：2024-07-25

申请号：US18626000

申请日：2024-04-03

Applicant: Imagination Technologies Limited

Inventor： Wei Shao ,  Christopher Wilson ,  Damien McNamara

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38 ,  G06F11/10 ,  G06F11/14 ,  G06F11/16 ,  G06F21/62 ,  G06F21/64

CPC classification number: G06F9/4843 ,  G06F9/30043 ,  G06F9/3877 ,  G06F11/1004 ,  G06F11/1497 ,  G06F11/1641 ,  G06F21/6245 ,  G06F21/64 ,  G06F2009/3883

Abstract: A graphics processing system for operation with a data store includes processing units for processing tasks. A check unit forms a signature which is characteristic of an output from processing a task on a processing unit, and a fault detection unit compares signatures formed at the check unit. The graphics processing system processes each task first and second times at the processing units so as to generate first and second processed outputs. The graphics processing system write outs the first processed output to the data store, reads back the first processed output from the data store and forms at the check unit a first signature characteristic of the first processed output as read back from the data store; forms at the check unit a second signature characteristic of the second processed output, compares the first and second signatures at the fault detection unit, and raises a fault signal if the signatures do not match.

公开(公告)号：US20240241695A1

公开(公告)日：2024-07-18

申请号：US18395836

申请日：2023-12-26

Applicant: Imagination Technologies Limited

Inventor： Leonard Rarick

IPC: G06F7/552 ,  G06F7/523 ,  G06F7/537

CPC classification number: G06F7/552 ,  G06F7/523 ,  G06F7/537 ,  G06F7/5525 ,  G06F2207/5351

Abstract: In an aspect, a processor includes circuitry for iterative refinement approaches, e.g., Newton-Raphson, to evaluating functions, such as square root, reciprocal, and for division. The circuitry includes circuitry for producing an initial approximation; which can include a LookUp Table (LUT). LUT may produce an output that (with implementation-dependent processing) forms an initial approximation of a value, with a number of bits of precision. A limited-precision multiplier multiplies that initial approximation with another value; an output of the limited precision multiplier goes to a full precision multiplier circuit that performs remaining multiplications required for iteration(s) in the particular refinement process being implemented. For example, in division, the output being calculated is for a reciprocal of the divisor. The full-precision multiplier circuit requires a first number of clock cycles to complete, and both the small multiplier and the initial approximation circuitry complete within the first number of clock cycles.

公开(公告)号：US12039667B2

公开(公告)日：2024-07-16

申请号：US16376511

申请日：2019-04-05

Applicant: Imagination Technologies Limited

Inventor： Peter Malcolm Lacey

IPC: G06T17/20 ,  G06T15/00 ,  G06T17/00 ,  G06T17/10

CPC classification number: G06T17/20 ,  G06T15/005 ,  G06T17/005 ,  G06T17/10 ,  G06T2200/28

Abstract: A method of generating identifiers (IDs) for primitives and optionally vertices during tessellation. The IDs include a binary sequence of bits that represents the sub-division steps taken during the tessellation process and so encodes the way in which tessellation has been performed. Such an ID may subsequently be used to generate a random primitive or vertex and hence recalculate vertex data for that primitive or vertex.

公开(公告)号：US20240233064A1

公开(公告)日：2024-07-11

申请号：US18394904

申请日：2023-12-22

Applicant: Imagination Technologies Limited

Inventor： Aroun Demeure ,  William Thomas ,  Alexander Hoffmann ,  Arturo Barrabes

IPC: G06T1/20 ,  G06T11/00

CPC classification number: G06T1/20 ,  G06T11/001 ,  G06T2210/52

Abstract: A method and processor for retrieving a block of data items, each being associated with a coordinate for each of dimensions of a stored data array. A data processing unit detects that the coordinates are axis-aligned. In response to detecting that the coordinates are axis-aligned, the following are sent to a data load unit: only one coordinate for a first dimension for each line of data items aligned in the first dimension within the block, and only one coordinate for a second dimension for each line of data items aligned in the second dimension within the block, the second dimension being orthogonal to the first dimension. The data load unit: (i) processes the coordinates to generate addresses of data array elements to be fetched from the stored data array, (ii) fetches data array elements using the generated addresses, (iii) determines data item values based on the fetched data array elements, and (iv) outputs the data item values.

公开(公告)号：US20240232596A1

公开(公告)日：2024-07-11

申请号：US18393320

申请日：2023-12-21

Applicant: Imagination Technologies Limited

Inventor： Xiran Huang

IPC: G06N3/063

CPC classification number: G06N3/063

Abstract: Methods of implementing a neural network in hardware, the neural network including a plurality of layers and the layers being grouped into a plurality of layer groups, each layer group comprising one or more layers of the neural network that are processed in a single pass through the hardware. The layer groups are grouped into a plurality of tile groups, each tile group comprising a set of layer groups that are evaluated when executing the neural network. The method comprises pre-fetching a portion of the input data for a first layer group in a tile group into a buffer slot in on-chip memory; and subsequently releasing the buffer slot after output data for the first layer group has been written to memory.

公开(公告)号：US12034934B2

公开(公告)日：2024-07-09

申请号：US18123148

申请日：2023-03-17

Applicant: Imagination Technologies Limited

Inventor： Ilaria Martinelli ,  Jeff Bond ,  Simon Fenney ,  Peter Malcolm Lacey ,  Gregory Clark

IPC: H04N19/00 ,  G06T1/20 ,  H04N19/132 ,  H04N19/176 ,  H04N19/42 ,  H04N19/89

CPC classification number: H04N19/132 ,  G06T1/20 ,  H04N19/176 ,  H04N19/42 ,  H04N19/89

Abstract: A method of converting 10-bit pixel data (e.g. 10:10:10:2 data) into 8-bit pixel data involves converting the 10-bit values to 7-bits or 8-bits and generating error values for each of the converted values. Two of the 8-bit output channels comprise a combination of a converted 7-bit value and one of the bits from the fourth input channel. A third 8-bit output channel comprises the converted 8-bit value and the fourth 8-bit output channel comprises the error values. In various examples, the bits of the error values may be interleaved when they are packed into the fourth output channel.