公开(公告)号：US07851333B2

公开(公告)日：2010-12-14

申请号：US11724603

申请日：2007-03-15

Applicant: Klaus-Guenter Oppermann ,  Martin Franosch ,  Martin Handtmann

Inventor： Klaus-Guenter Oppermann ,  Martin Franosch ,  Martin Handtmann

IPC: H01L21/00

CPC classification number: H03H9/02125 ,  H01L21/6835 ,  H01L23/3121 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68368 ,  H01L2224/0401 ,  H01L2224/11002 ,  H01L2224/16225 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An apparatus comprises a device layer structure, a device integrated into the device layer structure, an insulating carrier substrate and an insulating layer being continuously positioned between the device layer structure and the insulating carrier substrate, the insulating layer having a thickness which is less than 1/10 of a thickness of the insulating carrier substrate. An apparatus further comprises a device integrated into a device layer structure disposed on an insulating layer, a housing layer disposed on the device layer structure and housing the device, a contact providing an electrical connection between the device and a surface of the housing layer opposed to the device layer structure and a molding material surrounding the housing layer and the insulating layer, the molding material directly abutting on a surface of the insulating layer being opposed to the device layer structure.

Abstract translation: 一种装置包括器件层结构，集成到器件层结构中的器件，绝缘载体衬底和绝缘层，其连续地位于器件层结构和绝缘载体衬底之间，绝缘层的厚度小于1 绝缘载体基板的厚度的1/10。 一种装置还包括集成在设置在绝缘层上的器件层结构中的器件，设置在器件层结构上并容纳该器件的壳体层，提供该器件与壳体层相对的表面之间的电连接的触点 所述器件层结构和围绕所述壳体层和所述绝缘层的模制材料，所述模制材料直接邻接在所述绝缘层的与所述器件层结构相对的表面上。

公开(公告)号：US07682777B2

公开(公告)日：2010-03-23

申请号：US11387055

申请日：2006-03-22

Applicant: Martin Franosch ,  Andreas Meckes ,  Klaus-Guenter Oppermann

Inventor： Martin Franosch ,  Andreas Meckes ,  Klaus-Guenter Oppermann

IPC: G03F7/00

CPC classification number: B81B7/0048 ,  B81C2203/0136

Abstract: A method for producing a polymer structure on a patterning region of a substrate surface includes the steps of depositing an adhesion layer having a first polymer material onto the substrate surface, patterning the adhesion layer such that the first polymer material of the adhesion layer is removed in a first region and the first polymer material of the adhesion layer remains in a second region including the patterning region, depositing a polymer layer of a second polymer material onto the substrate surface and the adhesion layer and patterning the polymer layer such that the polymer structure forms in the second region.

Abstract translation: 在基板表面的图案化区域上制造聚合物结构的方法包括以下步骤：在基板表面上沉积具有第一聚合物材料的粘合层，图案化粘合层，使得粘合层的第一聚合物材料被去除 第一区域和粘合层的第一聚合物材料保留在包括图案化区域的第二区域中，将第二聚合物材料的聚合物层沉积到基底表面和粘合层上并且使聚合物层形成图案，使得聚合物结构形成 在第二个地区。

公开(公告)号：US20090295506A1

公开(公告)日：2009-12-03

申请号：US12130756

申请日：2008-05-30

Applicant: Martin Handtmann ,  Martin Franosch

Inventor： Martin Handtmann ,  Martin Franosch

IPC: H03H9/205 ,  H01L41/22

CPC classification number: H03H9/174 ,  H03H9/0207 ,  H03H9/02125 ,  H03H9/172 ,  H03H9/175 ,  H03H9/588 ,  H03H9/589 ,  Y10T29/42

Abstract: A BAW device includes a semiconductor substrate with a surface region, an insulating layer formed on the surface region and a piezoelectric layer sandwiched by a first and second electrode, wherein the second electrode is formed on the insulating layer. The surface region is performed such that a voltage dependence of a capacitance between the substrate and the second electrode is substantially suppressed.

Abstract translation: BAW器件包括具有表面区域的半导体衬底，形成在表面区域上的绝缘层和由第一和第二电极夹在中间的压电层，其中第二电极形成在绝缘层上。 执行表面区域，使得基板和第二电极之间的电容的电压依赖性被基本上抑制。

公开(公告)号：US07300823B2

公开(公告)日：2007-11-27

申请号：US10992627

申请日：2004-11-17

Applicant: Martin Franosch ,  Andreas Meckes ,  Winfried Nessler ,  Klaus-Gunter Oppermann

Inventor： Martin Franosch ,  Andreas Meckes ,  Winfried Nessler ,  Klaus-Gunter Oppermann

IPC: H01L21/00 ,  H01L21/76 ,  H01L21/30

CPC classification number: B81C1/00293 ,  B41J2/1603 ,  B41J2/1631 ,  B41J2/1632 ,  B41J2/1635 ,  B41J2/1639 ,  B41J2/1645 ,  B81B2201/0271 ,  B81C2203/0136 ,  B81C2203/0145 ,  Y10S438/977

Abstract: Apparatus for housing a micromechanical structure, and a method for producing the housing. The apparatus has a substrate having a main side on which the micromechanical structure is formed, a photo-resist material structure surrounding the micromechanical structure to form a cavity together with the substrate between the substrate and the photo-resist material structure, wherein the cavity separates the micromechanical structure and the photo-resist material structure and has an opening, and a closure for closing the opening to close the cavity.

Abstract translation: 用于容纳微机械结构的装置，以及用于制造外壳的方法。 该装置具有基板，其上形成有微机械结构的主侧面，围绕微机械结构的光致抗蚀剂材料结构，与基板和光刻胶材料结构之间的基板一起形成空腔，其中空腔分离 微机械结构和光致抗蚀剂材料结构并具有开口，以及用于封闭开口以封闭空腔的封闭件。

公开(公告)号：US07135757B2

公开(公告)日：2006-11-14

申请号：US10912344

申请日：2004-08-04

Applicant: Reinhard Stengl ,  Thomas Meister ,  Herbert Schäfer ,  Martin Franosch

Inventor： Reinhard Stengl ,  Thomas Meister ,  Herbert Schäfer ,  Martin Franosch

IPC: H01L27/082

CPC classification number: H01L29/66287 ,  H01L29/7322

Abstract: A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third layer is formed with an emitter cutout for an emitter. An undercut is formed in the second layer adjoining the base cutout. The base is at least partially located in the undercut. In order to obtain a low transition resistance between the lead and the base, an intermediate layer is provided between the first and the second layer. The intermediate layer is selectively etchable with respect to the second layer. At least in the region of the undercut between the lead and the base, a base connection zone is provided that can be adjusted independent of other production conditions. The intermediate layer is removed in a contact region with the base.

Abstract translation: 双极晶体管包括具有集电极的第一层。 第二层具有用于基座的基部切口。 第三层包括用于底座的引线。 第三层形成有用于发射极的发射极切口。 在与基座切口相邻的第二层中形成底切。 基部至少部分位于底切中。 为了在引线和基底之间获得低的过渡电阻，在第一和第二层之间设置中间层。 中间层相对于第二层可选择性地蚀刻。 至少在引线和基座之间的底切区域中，提供可以独立于其他生产条件进行调节的基础连接区域。 在与基底的接触区域中去除中间层。

公开(公告)号：US20060240643A1

公开(公告)日：2006-10-26

申请号：US11387055

申请日：2006-03-22

Applicant: Martin Franosch ,  Andreas Meckes ,  Klaus-Guenter Oppermann

Inventor： Martin Franosch ,  Andreas Meckes ,  Klaus-Guenter Oppermann

IPC: H01L21/30 ,  H01L21/46

CPC classification number: B81B7/0048 ,  B81C2203/0136

Abstract: A method for producing a polymer structure on a patterning region of a substrate surface includes the steps of depositing an adhesion layer having a first polymer material onto the substrate surface, patterning the adhesion layer such that the first polymer material of the adhesion layer is removed in a first region and the first polymer material of the adhesion layer remains in a second region including the patterning region, depositing a polymer layer of a second polymer material onto the substrate surface and the adhesion layer and patterning the polymer layer such that the polymer structure forms in the second region.

Abstract translation: 在基板表面的图案化区域上制造聚合物结构的方法包括以下步骤：在基板表面上沉积具有第一聚合物材料的粘合层，图案化粘合层，使得粘合层的第一聚合物材料被去除 第一区域和粘合层的第一聚合物材料保留在包括图案化区域的第二区域中，将第二聚合物材料的聚合物层沉积到基底表面和粘合层上并且使聚合物层形成图案，使得聚合物结构形成 在第二个地区。

公开(公告)号：US07064360B2

公开(公告)日：2006-06-20

申请号：US10470816

申请日：2002-02-04

Applicant: Martin Franosch ,  Thomas Meister ,  Herbert Schaefer ,  Reinhard Stengl

Inventor： Martin Franosch ,  Thomas Meister ,  Herbert Schaefer ,  Reinhard Stengl

IPC: H01L31/0328

CPC classification number: H01L29/66242 ,  H01L29/7378

Abstract: A method is provided to fabricate a bipolar transistor with a low base connection resistance, low defect density and improved scalability. Scalability is to be understood in this case as both the lateral scaling of the emitter window and the vertical scaling of the base width (low temperature budget). The temperature budget can be kept low in the base region since no implantations are required in order to reduce the base connection resistance. Furthermore, the difficulties associated with the point defects are largely avoided.

Abstract translation: 提供了一种制造具有低基极连接电阻，低缺陷密度和改进的可扩展性的双极晶体管的方法。 在这种情况下可以理解可扩展性，因为发射器窗口的横向缩放和基础宽度（低温预算）的垂直缩放。 由于不需要植入来降低基极连接电阻，所以在基极区域中的温度预算可以保持较低。 此外，很大程度上避免了与点缺陷相关的困难。

公开(公告)号：US06909141B2

公开(公告)日：2005-06-21

申请号：US10047013

申请日：2002-01-16

Applicant: Wolfgang Rösner ,  Thomas Schulz ,  Lothar Risch ,  Thomas Äugle ,  Herbert Schäfer ,  Martin Franosch

Inventor： Wolfgang Rösner ,  Thomas Schulz ,  Lothar Risch ,  Thomas Äugle ,  Herbert Schäfer ,  Martin Franosch

IPC: H01L21/335 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/76 ,  H01L51/00 ,  H01L51/05 ,  H01L51/30 ,  H01L21/8238

CPC classification number: B82Y10/00 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/7613 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0512

Abstract: A vertical semiconductor transistor component is built up on a substrate by using a statistical mask. The vertical semiconductor transistor component has vertical pillar structures statistically distributed over the substrate. The vertical pillar structures are electrically connected on a base side thereof to a first common electrical contact. The vertical pillar structures include, along the vertical direction, layer zones of differing conductivity, and have insulation layers on their circumferential walls. An electrically conductive material is deposited between the pillar structures and forms a second electrical contact of the semiconductor transistor component. The pillar structures are electrically contacted to a third common electrical contact on their capping side.

Abstract translation: 通过使用统计掩模在衬底上构建垂直半导体晶体管组件。 垂直半导体晶体管组件具有统计分布在衬底上的垂直柱结构。 垂直柱结构在其基极侧电连接到第一公共电接触。 垂直柱结构沿垂直方向包括不同导电性的层区，并且在其周壁上具有绝缘层。 导电材料沉积在柱结构之间并形成半导体晶体管组件的第二电接触。 支柱结构在其封盖侧与第三公共电触头电接触。

公开(公告)号：US06863769B2

公开(公告)日：2005-03-08

申请号：US10661340

申请日：2003-09-12

Applicant: Albert Birner ,  Martin Franosch ,  Matthias Goldbach ,  Volker Lehmann ,  Jörn Lützen

Inventor： Albert Birner ,  Martin Franosch ,  Matthias Goldbach ,  Volker Lehmann ,  Jörn Lützen

IPC: H01L21/00 ,  H01L21/306

CPC classification number: H01L21/67086 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A base body is provided, on which a first sealing ring and a second sealing ring are disposed. A substrate is disposed on the sealing rings in such a way that a cavity is formed between the first sealing ring, the second sealing ring, the base body and the substrate. An etching substance can be introduced into the cavity in order to etch clear a conductive layer that has been applied to the substrate. When a conductive layer that has been applied to the substrate back surface has been uncovered, an electrolyte can be introduced into the cavity, making contact with the conductive layer and therefore the substrate back surface.

Abstract translation: 设置有基体，其上设置有第一密封环和第二密封环。 基板被设置在密封环上，使得在第一密封环，第二密封环，基体和基底之间形成空腔。 可以将蚀刻物质引入到空腔中，以便对已经施加到基底上的导电层进行蚀刻。 当已经施加到基板背面的导电层未被覆盖时，可以将电解质引入空腔中，与导电层接触，从而与基板背面接触。

公开(公告)号：US20050048757A1

公开(公告)日：2005-03-03

申请号：US10888568

申请日：2004-07-09

Applicant: Robert Aigner ,  Martin Franosch ,  Andreas Meckes ,  Klaus-Gunter Oppermann ,  Marc Strasser

Inventor： Robert Aigner ,  Martin Franosch ,  Andreas Meckes ,  Klaus-Gunter Oppermann ,  Marc Strasser

IPC: B81B7/00 ,  B81C1/00 ,  H03H3/02 ,  H01L21/44

CPC classification number: B81C1/00293 ,  B81C2203/0136 ,  B81C2203/0145 ,  H03H3/02

Abstract: In a method for generating a protective cover for a device, where a substrate is provided, which comprises the device, first, a sacrificial pattern is generated on the substrate. The sacrificial pattern covers at least an area of the substrate, which comprises the device. Then, a polymer layer is deposited, which comprises at least on sacrificial pattern. Then, an opening will be formed in the polymer layer to expose a portion of the sacrificial pattern. Then, the sacrificial pattern will be removed and the formed opening in the polymer layer is closed.