公开(公告)号：US09412412B2

公开(公告)日：2016-08-09

申请号：US14521326

申请日：2014-10-22

Applicant: SILICON GRAPHICS INTERNATIONAL CORP.

Inventor： Kevan Flint Rehm ,  Judith Ann Schmitz ,  Joseph Carl Nemeth ,  John Michael Sygulla

IPC: G11B5/584 ,  G11B20/12 ,  G11B20/18 ,  G11B5/008

CPC classification number: G06F11/1004 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0682 ,  G11B5/00813 ,  G11B20/1202 ,  G11B20/1833 ,  G11B2020/1843

Abstract: A two part process is used for modifying records to be written and retrieved from tape devices. A record is appended with a cyclic redundancy check and a string of zeros. Submitting the entire record to tape drives which are logical block protection enabled will result in no change. For drives that are not LBP enabled, the string of zeros at the end of the record is removed. In addition to determining whether a drive is LBP compliant, a determination may be made as to whether a drive is a linear tape open drive from a particular manufacturer. Linear tape open drives may behave similarly as drives which may not be enabled with logical block protection.

Abstract translation: 用于修改要从磁带设备写入和检索的记录的两部分过程。 一个记录附加一个循环冗余校验和一串零。 将整个记录提交到启用了逻辑块保护的磁带驱动器将导致无变化。 对于不启用LBP的驱动器，删除记录末尾的零字符串。 除了确定驱动器是否符合LBP之外，还可以确定驱动器是否是来自特定制造商的线性磁带打开驱动器。 线性磁带打开驱动器可能与可能未启用逻辑块保护的驱动器类似。

公开(公告)号：US09389940B2

公开(公告)日：2016-07-12

申请号：US13780248

申请日：2013-02-28

Applicant: Silicon Graphics International Corp.

Inventor： Mark Larson ,  Michael Brown ,  Gary Meyer

IPC: G06F11/00 ,  G06F11/07

CPC classification number: G06F11/0772 ,  G06F11/0724 ,  G06F11/25

Abstract: Error data is read from error registers and written into a buffer. A computing node uses a BIOS to read the error data, rearm the error register and write the data into a memory mapped buffer. A hub chip supports creation of a shared memory system of computing nodes. A management controller in the computing node extracts error data from the buffer. The error data preferably consists essentially of the error register identifiers and the contents of the error registers. A system management node receives the error data from the management controllers in the computing nodes. The system management node may be coupled to but separate from the computing nodes.

Abstract translation: 错误数据从错误寄存器中读取并写入缓冲区。 计算节点使用BIOS读取错误数据，重新设置错误寄存器并将数据写入存储器映射缓冲区。 集线器芯片支持创建计算节点的共享存储器系统。 计算节点中的管理控制器从缓冲器中提取错误数据。 错误数据优选地基本上由错误寄存器标识符和错误寄存器的内容组成。 系统管理节点从计算节点中的管理控制器接收错误数据。 系统管理节点可以耦合到但是与计算节点分离。

公开(公告)号：US09389760B2

公开(公告)日：2016-07-12

申请号：US13931818

申请日：2013-06-29

Applicant: Silicon Graphics International Corp.

Inventor： Eng Lim Goh ,  Hansong Zhang ,  Chandrasekhar Murthy

IPC: G06F3/048 ,  G06F3/0484 ,  G06F9/44 ,  G06F11/36

CPC classification number: G06F9/4445 ,  G06F3/0484 ,  G06F9/451 ,  G06F9/452 ,  G06F11/3636 ,  G06T11/206

Abstract: A system may provide a visualization function during computational functions performed by a host system. Access to a library of functions including a visualization function is provided. Then, a computing application is executed. The execution of the computing application includes generating multi-dimensional data, invoking the visualization function from the library, and providing a visual representation of at least a portion of the multi-dimensional data for display within the computing application using the visualization function.

Abstract translation: 系统可以在由主机系统执行的计算功能期间提供可视化功能。 提供对包括可视化功能的功能库的访问。 然后，执行计算应用。 计算应用的执行包括生成多维数据，从库调用可视化功能，以及使用该可视化功能提供用于在计算应用内显示的多维数据的至少一部分的视觉表示。

公开(公告)号：US09367473B2

公开(公告)日：2016-06-14

申请号：US14141326

申请日：2013-12-26

Applicant: Silicon Graphics International, Corp.

Inventor： Jeffrey S. Kuskin

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0804 ,  G06F12/0813 ,  G06F12/0822 ,  G06F12/0842 ,  G06F12/0891 ,  G06F12/1491

Abstract: A processor (600) in a distributed shared memory multi-processor computer system (10) may initiate a flush request to remove data from its cache. A processor interface (24) receives the flush request and performs a snoop operation to determine whether the data is maintained in a one of the local processors (601) and whether the data has been modified. If the data is maintained locally and it has been modified, the processor interface (24) initiates removal of the data from the cache of the identified processor (601). The identified processor (601) initiates a writeback to a memory directory interface unit (24) associated with a home memory 17 for the data in order to preserve the modification to the data. If the data is not maintained locally or has not been modified, the processor interface (24) forwards the flush request to the memory directory interface unit (22). Memory directory interface unit (22) determines which remote processors within the system (10) have a copy of the data and forwards the flush request only to those identified processors. The identified processors then remove the data from their respective caches in response to the flush request. If an identified remote processor has modified data, the identified remote processor initiates a writeback to the memory directory interface unit (22) for preservation of the modified data.

Abstract translation: 在分布式共享存储器多处理器计算机系统（10）中的处理器（600）可以发起刷新请求以从其高速缓存中移除数据。 处理器接口（24）接收刷新请求并执行窥探操作以确定数据是否保持在本地处理器（601）之一以及数据是否被修改。 如果数据在本地维护并且已经被修改，则处理器接口（24）启动从所识别的处理器（601）的高速缓存中移除数据。 所识别的处理器（601）发起与用于数据的归属存储器17相关联的存储器目录接口单元（24）的回写，以便保留对数据的修改。 如果数据未在本地维护或未被修改，则处理器接口（24）将刷新请求转发到存储器目录接口单元（22）。 存储器目录接口单元（22）确定系统（10）内的哪些远程处理器具有数据的副本，并将刷新请求仅转发到那些已识别的处理器。 然后，所识别的处理器响应于刷新请求从其各自的高速缓存中移除数据。 如果所识别的远程处理器具有修改的数据，则所识别的远程处理器发起对存储器目录接口单元（22）的回写以保存修改的数据。

公开(公告)号：US09252812B2

公开(公告)日：2016-02-02

申请号：US14229796

申请日：2014-03-28

Applicant: Silicon Graphics International Corp.

Inventor： Mark Ronald Sikkink ,  John Francis De Ryckere

IPC: H03M13/00 ,  H03M13/17 ,  H03M13/09 ,  H04L1/00 ,  H03M13/11

CPC classification number: H03M13/17 ,  H03M13/09 ,  H03M13/11 ,  H04L1/0057 ,  H04L1/0061 ,  H04L1/0079 ,  H04L1/0083 ,  H04L25/14 ,  H04L25/4908

Abstract: A high performance computing system and method communicate data packets between computing nodes on a multi-lane communications link using a modified header bit encoding. Each data packet is provided with flow control information and error detection information, then divided into per-lane payloads. Sync header bits for each payload are added to the payloads in non-adjacent locations, thereby decreasing the probability that a single correlated burst error will invert both header bits. The encoded blocks that include the payload and the interspersed header bits are then simultaneously transmitted on the multiple lanes for reception, error detection, and reassembly by a receiving computing node.

Abstract translation: 高性能计算系统和方法使用修改的报头位编码在多通道通信链路上的计算节点之间传送数据分组。 每个数据包都提供流量控制信息和错误检测信息，然后划分为每通道有效载荷。 每个有效载荷的同步头位被添加到非相邻位置中的有效载荷，从而降低单个相关突发错误将颠倒两个标题位的概率。 然后，在多个通道上同时发送包含有效载荷和散布的报头位的编码块，以便接收计算节点进行接收，错误检测和重组。

公开(公告)号：US09229661B2

公开(公告)日：2016-01-05

申请号：US13897215

申请日：2013-05-17

Applicant: Silicon Graphics International Corp.

Inventor： Kevan Flint Rehm ,  Benjamin Paul Myers

IPC: G06F12/00 ,  G06F3/06 ,  G06F11/14

CPC classification number: G06F3/0689 ,  G06F3/0617 ,  G06F3/0653 ,  G06F11/1448

Abstract: Quotas are tracked for user usage of hard disk drive space and offline backup storage space. The quota is enforced against the total space utilized by a user, not just high tier hard drive space usage. When data is migrated from hard disk drive space to backup storage space, data metadata is updated to reflect data kept offline for the user. As such, when users request to store new data, the data usage of hard disk space and backup storage space is determined from the metadata that reflects both data types, and the total storage spaced for the user is used to grant or reject the user's request to store more data in the system.

Abstract translation: 跟踪用户使用硬盘驱动器空间和脱机备份存储空间的配额。 配额是针对用户使用的总空间执行的，而不仅仅是高层硬盘空间的使用。 当数据从硬盘驱动器空间迁移到备份存储空间时，数据元数据将被更新，以反映用户不断离线的数据。 因此，当用户请求存储新数据时，从反映这两种数据类型的元数据确定硬盘空间和备份存储空间的数据使用，并且用于用户的总存储空间用于授予或拒绝用户的请求 在系统中存储更多的数据。

公开(公告)号：US09208090B2

公开(公告)日：2015-12-08

申请号：US14012783

申请日：2013-08-28

Applicant: Silicon Graphics International Corp.

Inventor： Eric Fromm

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/16 ,  G06F9/46 ,  G06F3/00

CPC classification number: G06F12/0828 ,  G06F9/467 ,  G06F12/0813 ,  G06F12/0831 ,  G06F12/084 ,  G06F13/16

Abstract: Processors in a compute node offload transactional memory accesses addressing shared memory to a transactional memory agent. The transactional memory agent typically resides near the processors in a particular compute node. The transactional memory agent acts as a proxy for those processors. A first benefit of the invention includes decoupling the processor from the direct effects of remote system failures. Other benefits of the invention includes freeing the processor from having to be aware of transactional memory semantics, and allowing the processor to address a memory space larger than the processor's native hardware addressing capabilities. The invention also enables computer system transactional capabilities to scale well beyond the transactional capabilities of those found computer systems today.

Abstract translation: 计算节点卸载事务内存中的处理器访问寻址共享内存到事务内存代理。 事务内存代理通常驻留在特定计算节点中的处理器附近。 事务内存代理充当这些处理器的代理。 本发明的第一个优点包括使处理器与远程系统故障的直接影响相分离。 本发明的其他优点包括释放处理器不必意识到事务性存储器语义，并允许处理器寻址大于处理器本机硬件寻址能力的存储器空间。 本发明还使得计算机系统的事务能力能够远远超出目前那些找到的计算机系统的事务能力。

公开(公告)号：US09176669B2

公开(公告)日：2015-11-03

申请号：US13833956

申请日：2013-03-15

Applicant: Silicon Graphics International Corp.

Inventor： Brian Justin Johnson ,  Michael John Habeck

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/06 ,  G06F12/0284 ,  G06F12/063

Abstract: An algorithm for mapping memory and a method for using a high performance computing (“HPC”) system are disclosed. The algorithm takes into account the number of physical nodes in the HPC system, and the amount of memory in each node. Some of the nodes in the HPC system also include input/output (“I/O”) devices like graphics cards and non-volatile storage interfaces that have on-board memory; the algorithm also accounts for the number of such nodes and the amount of I/O memory they each contain. The algorithm maximizes certain parameters in priority order, including the number of mapped nodes, the number of mapped I/O nodes, the amount of mapped I/O memory, and the total amount of mapped memory.

Abstract translation: 公开了一种用于映射存储器的算法和一种使用高性能计算（“HPC”）系统的方法。 该算法考虑了HPC系统中物理节点的数量以及每个节点中的内存量。 HPC系统中的一些节点还包括输入/​​输出（“I / O”）设备，如显卡和具有板上存储器的非易失性存储接口; 该算法还考虑了这些节点的数量以及它们各自包含的I / O存储器的数量。 该算法使优先级顺序中的某些参数最大化，包括映射节点的数量，映射的I / O节点的数量，映射的I / O存储器的数量以及映射的存储器总量。

公开(公告)号：US20150280746A1

公开(公告)日：2015-10-01

申请号：US14229796

申请日：2014-03-28

Applicant: Silicon Graphics International Corp.

Inventor： Mark Ronald Sikkink ,  John Francis De Ryckere

IPC: H03M13/17 ,  H03M13/09

CPC classification number: H03M13/17 ,  H03M13/09 ,  H03M13/11 ,  H04L1/0057 ,  H04L1/0061 ,  H04L1/0079 ,  H04L1/0083 ,  H04L25/14 ,  H04L25/4908

Abstract: A high performance computing system and method communicate data packets between computing nodes on a multi-lane communications link using a modified header bit encoding. Each data packet is provided with flow control information and error detection information, then divided into per-lane payloads. Sync header bits for each payload are added to the payloads in non-adjacent locations, thereby decreasing the probability that a single correlated burst error will invert both header bits. The encoded blocks that include the payload and the interspersed header bits are then simultaneously transmitted on the multiple lanes for reception, error detection, and reassembly by a receiving computing node.

Abstract translation: 高性能计算系统和方法使用修改的报头位编码在多通道通信链路上的计算节点之间传送数据分组。 每个数据包都提供流量控制信息和错误检测信息，然后划分为每通道有效载荷。 每个有效载荷的同步头位被添加到非相邻位置中的有效载荷，从而降低单个相关突发错误将颠倒两个标题位的概率。 然后，在多个通道上同时发送包含有效载荷和散布的报头位的编码块，以便接收计算节点进行接收，错误检测和重组。

公开(公告)号：US09117288B2

公开(公告)日：2015-08-25

申请号：US14528929

申请日：2014-10-30

Applicant: Silicon Graphics International Corp.

Inventor： Alexander Chalfin ,  Alpana Kaulgud ,  Mark Peercy

IPC: H04L29/06 ,  G06T1/20 ,  G06T15/00

CPC classification number: G06T1/20 ,  G06T15/00 ,  G06T2200/16 ,  H04L69/16 ,  H04L69/165

Abstract: A system and method for remote rendering of computer graphics wherein user transactions are reliable and the transmission of rendered graphics is relatively fast. The invention is implemented in a client server context, where a computer graphics application and rendering resources are located at a server. A user controls the graphics application through a client machine connected to the server through a computer network. The user's commands are sent from the client to the server, while rendered computer graphics are transmitted from the server to a display at the client. Different transport protocols are used, depending on the requirements of a particular transmission. Data related to user interactions is transmitted using a relatively reliable transport protocol, such as TCP. Rendered subject graphics data is transmitted from the server to the client using a less reliable but faster transport protocol, such UDP.

Abstract translation: 用于远程呈现计算机图形的系统和方法，其中用户事务是可靠的并且渲染图形的传输相对较快。 本发明在客户端服务器上下文中实现，其中计算机图形应用程序和呈现资源位于服务器处。 用户通过计算机网络通过连接到服务器的客户机来控制图形应用程序。 用户的命令从客户端发送到服务器，而将计算机图形从服务器传输到客户端的显示器。 根据特定传输的要求，使用不同的传输协议。 使用比较可靠的传输协议（如TCP）传输与用户交互相关的数据。 渲染的主题图形数据从服务器传输到客户端，使用不太可靠但更快速的传输协议，如UDP。