公开(公告)号：US09972575B2

公开(公告)日：2018-05-15

申请号：US15060224

申请日：2016-03-03

Applicant: APPLIED MATERIALS, INC.

Inventor： Jungrae Park ,  Wei-Sheng Lei ,  Brad Eaton ,  James S. Papanu ,  Ajay Kumar

IPC: H01L21/78 ,  H01L23/544 ,  B23K26/0622 ,  B23K10/00 ,  A47G19/22 ,  B65D47/24 ,  B65D47/32

CPC classification number: H01L23/544 ,  A47G19/22 ,  A47G19/2272 ,  B23K10/003 ,  B23K26/0624 ,  B65D47/244 ,  B65D47/32 ,  H01L21/78 ,  H01L2223/5446

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a split laser beam laser scribing process, such as a split shaped laser beam laser scribing process, to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

公开(公告)号：US09852997B2

公开(公告)日：2017-12-26

申请号：US15081296

申请日：2016-03-25

Applicant: APPLIED MATERIALS, INC.

Inventor： Jungrae Park ,  Wei-Sheng Lei ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

IPC: H01L21/00 ,  H01L23/544 ,  H01L21/78 ,  B23K26/359 ,  B23K26/064 ,  B23K26/364

CPC classification number: B23K26/064 ,  B23K26/0006 ,  B23K26/0624 ,  B23K26/355 ,  B23K26/359 ,  B23K26/364 ,  B23K26/402 ,  B23K2101/40 ,  B23K2101/42 ,  H01L21/78

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a rotating laser beam laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

公开(公告)号：US09620379B2

公开(公告)日：2017-04-11

申请号：US14775651

申请日：2014-03-11

Applicant: APPLIED MATERIALS, INC.

Inventor： Wei-Sheng Lei ,  Mohammad Kamruzzaman Chowdhury ,  Todd Egan ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Ajay Kumar

IPC: H01L21/67 ,  H01L21/78 ,  H01L21/308 ,  H01L21/3065 ,  B23K26/364 ,  B23K26/40 ,  B23K26/402 ,  H01L21/673 ,  H01L21/687 ,  H01L21/82 ,  B23K103/16 ,  B23K103/00

CPC classification number: H01L21/3086 ,  B23K26/364 ,  B23K26/40 ,  B23K26/402 ,  B23K2103/172 ,  B23K2103/50 ,  B23K2103/56 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/67069 ,  H01L21/67196 ,  H01L21/67207 ,  H01L21/67383 ,  H01L21/68707 ,  H01L21/78 ,  H01L21/82

Abstract: Methods of dicing substrates having a plurality of ICs. A method includes forming a multi-layered mask comprising a laser energy absorbing, non-photodefinable topcoat disposed over a water-soluble base layer disposed over the semiconductor substrate. Because the laser light absorbing material layer is non-photodefinable, material costs associated with conventional photo resist formulations may be avoided. The mask is direct-write patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the substrate between the ICs. Absorption of the mask layer within the laser emission band (e.g., UV band and/or green band) promotes good scribe line quality. The substrate may then be plasma etched through the gaps in the patterned mask to singulate the IC with the mask protecting the ICs during the plasma etch. The soluble base layer of the mask may then be dissolved subsequent to singulation, facilitating removal of the layer.

公开(公告)号：US09343366B2

公开(公告)日：2016-05-17

申请号：US14543747

申请日：2014-11-17

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  James S. Papanu ,  Aparna Iyer ,  Brad Eaton ,  Ajay Kumar

IPC: H01L21/00 ,  H01L21/78 ,  H01L21/683 ,  H01L21/268 ,  H01L21/3065 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L21/78 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/6836 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/12041 ,  H01L2224/11 ,  H01L2924/00

Abstract: Approaches for hybrid laser scribe and plasma etch dicing process for a wafer having backside solder bumps are described. For example, a method of dicing a semiconductor wafer having integrated circuits on a front side thereof and corresponding arrays of metal bumps on a backside thereof involves applying a dicing tape to the backside of the semiconductor wafer, the dicing tape covering the arrays of metal bumps. The method also involves, subsequently, forming a mask on the front side of the semiconductor wafer, the mask covering the integrated circuits. The method also involves forming scribe lines on the front side of the semiconductor wafer with a laser scribing process, the scribe lines formed in the mask and between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the scribe lines to singulate the integrated circuits, the mask protecting the integrated circuits during the plasma etching.

Abstract translation: 描述了具有背面焊料凸块的晶片的混合激光划片和等离子体蚀刻切割工艺的方法。 例如，在其前侧具有集成电路的半导体晶片的切割方法和背面的金属凸块的相应阵列包括在半导体晶片的背面施加切割带，该切割带覆盖金属凸块的阵列 。 该方法还包括在半导体晶片的正面上形成掩模，该掩模覆盖集成电路。 该方法还涉及通过激光划线工艺在半导体晶片的正面上形成刻划线，在掩模中形成划线并在集成电路之间。 该方法还包括通过划线等离子体蚀刻半导体晶片以对集成电路进行分离，掩模在等离子体蚀刻期间保护集成电路。

公开(公告)号：US09280051B2

公开(公告)日：2016-03-08

申请号：US14301835

申请日：2014-06-11

Applicant: APPLIED MATERIALS, INC.

Inventor： Banqiu Wu ,  Ajay Kumar ,  Rao Yalamanchili ,  Omkaram Nalamasu

IPC: H01L21/302 ,  G03F7/26 ,  H01L21/308 ,  H01L21/027

CPC classification number: G03F7/26 ,  H01L21/0273 ,  H01L21/3086

Abstract: Methods for reducing line width roughness and/or critical dimension nonuniformity in a photoresist pattern are provided herein. In some embodiments, a method of reducing line width roughness along a sidewall of a patterned photoresist layer disposed atop a substrate includes: (a) depositing a first layer atop the sidewall of the patterned photoresist layer; (b) etching the first layer and the sidewall after depositing the first layer to reduce the line width roughness of the patterned photoresist layer. In some embodiments, (a)-(b) may be repeated until the line width roughness is substantially smooth.

Abstract translation: 本文提供了减少光致抗蚀剂图案中的线宽粗糙度和/或临界尺寸不均匀性的方法。 在一些实施例中，沿着设置在衬底顶部的图案化光致抗蚀剂层的侧壁减小线宽度粗糙度的方法包括：（a）在图案化光致抗蚀剂层的侧壁顶部沉积第一层; （b）在沉积第一层之后蚀刻第一层和侧壁以减小图案化光致抗蚀剂层的线宽粗糙度。 在一些实施例中，（a） - （b）可以重复，直到线宽粗糙度基本上平滑。

公开(公告)号：US09070633B2

公开(公告)日：2015-06-30

申请号：US14284088

申请日：2014-05-21

Applicant: Applied Materials, Inc.

Inventor： Roy C. Nangoy ,  Saravjeet Singh ,  Jon C. Farr ,  Sharma V. Pamarthy ,  Ajay Kumar

IPC: B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01L21/3065 ,  H01J37/32 ,  C23C16/455 ,  C23C16/505 ,  H01L21/67

CPC classification number: H01L21/3065 ,  C23C16/45508 ,  C23C16/45563 ,  C23C16/45574 ,  C23C16/45587 ,  C23C16/45591 ,  C23C16/505 ,  H01J37/321 ,  H01J37/3211 ,  H01J37/3222 ,  H01J37/3244 ,  H01J37/32449 ,  H01J37/32458 ,  H01L21/30655 ,  H01L21/67069

Abstract: Embodiments of the present disclosure relate to method and apparatus for providing processing gases to a process chamber with improved plasma dissociation efficiency. One embodiment of the present disclosure provides a baffle nozzle assembly comprising an outer body defining an extension volume connected to a processing chamber. A processing gas is flown to the processing chamber through the extension volume which is exposed to power source for plasma generation.

Abstract translation: 本公开的实施例涉及用于向具有改进的等离子体解离效率的处理室提供处理气体的方法和装置。 本公开的一个实施例提供了一种挡板喷嘴组件，其包括限定连接到处理室的延伸体的外部主体。 处理气体通过暴露于等离子体产生的电源的延伸体积流到处理室。

公开(公告)号：US08969177B2

公开(公告)日：2015-03-03

申请号：US13917568

申请日：2013-06-13

Applicant: Applied Materials, Inc.

Inventor： Mohammad Kamruzzaman Chowdhury ,  Wei-Sheng Lei ,  Todd Egan ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Ajay Kumar

IPC: H01L21/00 ,  H01L21/78 ,  B23K26/36 ,  H01L21/67 ,  B23K26/06 ,  B23K26/18 ,  B23K26/40

CPC classification number: H01L21/67155 ,  B23K26/0624 ,  B23K26/0661 ,  B23K26/18 ,  B23K26/361 ,  B23K26/40 ,  B23K2101/40 ,  B23K2103/172 ,  B23K2103/50 ,  H01L21/67069 ,  H01L21/67115 ,  H01L21/67207 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/68381

Abstract: Laser and plasma etch wafer dicing using UV-curable adhesive films. A mask is formed covering ICs formed on the wafer, as well as any bumps providing an interface to the ICs. The semiconductor wafer is coupled to a carrier substrate by a double-sided UV-curable adhesive film. The mask is patterned by laser scribing to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer, below thin film layers from which the ICs are formed. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the ICs. The UV-curable adhesive film is partially cured by UV irradiation through the carrier. The singulated ICs are then detached from the partially cured adhesive film still attached to the carrier substrate, for example individually by a pick and place machine. The UV-curable adhesive film may then be further cured for the film's complete removal from the carrier substrate.

Abstract translation: 激光和等离子体蚀刻晶圆切割使用紫外光固化粘合膜。 形成覆盖在晶片上形成的IC的掩模，以及提供与IC的接口的任何凸块。 半导体晶片通过双面UV固化粘合剂膜耦合到载体基板。 通过激光划线将掩模图案化以提供具有间隙的图案化掩模。 图案化使得半导体晶片的区域在形成IC的薄膜层之下露出。 然后通过图案化掩模中的间隙蚀刻半导体晶片，以对IC进行单片化。 UV固化粘合剂膜通过载体的UV照射部分固化。 然后将分离的IC从仍然附着到载体基底上的部分固化的粘合剂膜分离，例如通过拾取和放置机单独分离。 然后可以进一步固化可UV固化的粘合剂膜，以使膜完全从载体基材上除去。

公开(公告)号：US11621194B2

公开(公告)日：2023-04-04

申请号：US17137099

申请日：2020-12-29

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC: H01J37/00 ,  H01L21/822 ,  H01L21/308 ,  H01L21/67 ,  H01L21/78 ,  H01J37/32 ,  H01L23/544 ,  B23K26/36 ,  H01L21/3065 ,  H01L21/683

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

公开(公告)号：US10910271B2

公开(公告)日：2021-02-02

申请号：US16885142

申请日：2020-05-27

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC: H01L21/00 ,  H01L21/822 ,  H01L21/308 ,  H01L21/67 ,  H01L21/78 ,  H01J37/32 ,  H01L23/544 ,  B23K26/36 ,  H01L21/3065 ,  H01L21/683

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

公开(公告)号：US10714390B2

公开(公告)日：2020-07-14

申请号：US16706541

申请日：2019-12-06

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC: H01L21/00 ,  H01L21/822 ,  H01L21/3065 ,  B23K26/36 ,  H01L23/544 ,  H01L21/67 ,  H01J37/32 ,  H01L21/78 ,  H01L21/308 ,  H01L21/683

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.