中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

61 records (took 0.026 seconds)

    Integrated Circuit with Laminated Magnetic Core Inductor and Magnetic Flux Closure Layer
    51.
    发明申请
    Integrated Circuit with Laminated Magnetic Core Inductor and Magnetic Flux Closure Layer 有权

    公开(公告)号：US20210321518A1

    公开(公告)日：2021-10-14

    申请号：US17358318

    申请日：2021-06-25

    Applicant: Ferric Inc.

    Inventor： Noah Sturcken ,  Ryan Davies ,  Michael Lekas

    IPC: H05K1/18 ,  H01F41/04 ,  H01F41/02 ,  H01F27/28 ,  H01F27/24 ,  H05K1/02 ,  H05K1/11 ,  H01F17/00 ,  H01F41/32

    Abstract: A structure comprises a semiconductor integrated circuit, an inductor, and a magnetic flux closure layer. The inductor is integrated into a multilevel wiring network in the semiconductor integrated circuit. The inductor includes a planar laminated magnetic core and a conductive winding that turns around in a generally spiral manner on the outside of the planar laminated magnetic core. The planar laminated magnetic core includes an alternating sequence of a magnetic layer and a non-magnetic layer. The magnetic flux closure layer is disposed within about 100 μm of a face of the planar laminated magnetic core, the face of the planar magnetic core parallel to a principal plane of the planar laminated magnetic core. A second magnetic flux closure layer can be disposed within about 100 μm of an opposing face of the planar laminated magnetic core.

    Zero-voltage switch-mode power converter
    54.
    发明授权
    Zero-voltage switch-mode power converter 有权

    公开(公告)号：US10326366B2

    公开(公告)日：2019-06-18

    申请号：US15869726

    申请日：2018-01-12

    Applicant: Ferric Inc.

    Inventor： William Lee ,  David Jew ,  Joseph Meyer ,  Noah Sturcken

    IPC: H02M3/158 ,  H02M3/157 ,  H02M1/38 ,  H02M1/00

    Abstract: A switched-mode power converter includes timing control feedback loop circuits to minimize or eliminate the potential difference across a high-power switch and a low-power switch during their transitions times. A first feedback circuit compares the measured voltage across the high-power switch at the moment the high-power switch closes with the input voltage to the high-power switch to control a low-to-high delay time. A second feedback circuit compares the measured voltage across the low-power switch at the moment the low-power switch closes with the input voltage to the low-power switch to control a high-to-low delay time. A third feedback circuit compares the measured voltage across the low-power switch at the moment the low-power switch opens. The output of the third feedback circuit is provided as inputs to the first and second feedback circuits. The third feedback circuit also controls the frequency of the power converter.

    Laminated Magnetic Core Inductor with Magnetic Flux Closure Path Parallel to Easy Axes of Magnetization of Magnetic Layers
    56.
    发明申请
    Laminated Magnetic Core Inductor with Magnetic Flux Closure Path Parallel to Easy Axes of Magnetization of Magnetic Layers 审中-公开

    公开(公告)号：US20180302986A1

    公开(公告)日：2018-10-18

    申请号：US16007569

    申请日：2018-06-13

    Applicant: Ferric Inc.

    Inventor： Noah Sturcken ,  Ryan Davies ,  Michael Lekas

    IPC: H05K1/18 ,  H01F41/02 ,  H01F27/28 ,  H01F27/24 ,  H05K1/16 ,  H05K1/02

    Abstract: An inductor comprises a planar laminated magnetic core and a conductive winding. The core includes an alternating sequence of (a) a magnetic layer having a thickness of about 100 angstroms to about 10,000 angstroms and (b) a non-magnetic layer having a thickness of about 10 angstroms to about 2,000 angstroms. Magnetic flux passes through a first magnetic layer parallel to a first easy axis of magnetization of the first magnetic layer and the magnetic flux passes through a second magnetic layer, disposed adjacent to the first magnetic layer, parallel to a second easy axis of magnetization of the second magnetic layer. The magnetic flux path extends through the first and second magnetic layers parallel to the first and second easy axes of magnetization, respectively. At least one orthogonal magnetic layer can be disposed laterally from the core such that the magnetic flux path extends through the orthogonal magnetic layer(s).

    Integrated Circuit with Laminated Magnetic Core Inductor and Magnetic Flux Closure Layer
    57.
    发明申请
    Integrated Circuit with Laminated Magnetic Core Inductor and Magnetic Flux Closure Layer 审中-公开

    公开(公告)号：US20180295726A1

    公开(公告)日：2018-10-11

    申请号：US16007631

    申请日：2018-06-13

    Applicant: Ferric Inc.

    Inventor： Noah Sturcken ,  Ryan Davies ,  Michael Lekas

    IPC: H05K1/18 ,  H01F41/02 ,  H01F27/28 ,  H01F27/24 ,  H05K1/16 ,  H05K1/02

    Abstract: A structure comprises a semiconductor integrated circuit, an inductor, and a magnetic flux closure layer. The inductor is integrated into a multilevel wiring network in the semiconductor integrated circuit. The inductor includes a planar laminated magnetic core and a conductive winding that turns around in a generally spiral manner on the outside of the planar laminated magnetic core. The planar laminated magnetic core includes an alternating sequence of a magnetic layer and a non-magnetic layer. The magnetic flux closure layer is disposed within about 100 μm of a face of the planar laminated magnetic core, the face of the planar magnetic core parallel to a principal plane of the planar laminated magnetic core. A second magnetic flux closure layer can be disposed within about 100 μm of an opposing face of the planar laminated magnetic core.

    Zero-Voltage Switch-Mode Power Converter
    59.
    发明申请
    Zero-Voltage Switch-Mode Power Converter 审中-公开

    公开(公告)号：US20180145592A1

    公开(公告)日：2018-05-24

    申请号：US15869726

    申请日：2018-01-12

    Applicant: Ferric Inc.

    Inventor： William Lee ,  David Jew ,  Joseph Meyer ,  Noah Sturcken

    IPC: H02M3/158 ,  H02M3/157 ,  H02M1/00

    CPC classification number: H02M3/158 ,  H02M1/38 ,  H02M3/157 ,  H02M3/1588 ,  H02M2001/0058 ,  Y02B70/1466 ,  Y02B70/1491

    Abstract: A switched-mode power converter includes timing control feedback loop circuits to minimize or eliminate the potential difference across a high-power switch and a low-power switch during their transitions times. A first feedback circuit compares the measured voltage across the high-power switch at the moment the high-power switch closes with the input voltage to the high-power switch to control a low-to-high delay time. A second feedback circuit compares the measured voltage across the low-power switch at the moment the low-power switch closes with the input voltage to the low-power switch to control a high-to-low delay time. A third feedback circuit compares the measured voltage across the low-power switch at the moment the low-power switch opens. The output of the third feedback circuit is provided as inputs to the first and second feedback circuits. The third feedback circuit also controls the frequency of the power converter.

Patent Agency Ranking