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公开(公告)号：US11197374B2
公开(公告)日：2021-12-07
申请号：US16279574
申请日：2019-02-19
Applicant: Ferric Inc.
Inventor： Noah Sturcken , Joseph Meyer , Michael Lekas , Ryan Davies , David Jew , William Lee
IPC: H02M3/158 , H05K1/18 , H05K1/11 , H05K1/02 , H01F27/24 , H01F27/28 , H01F41/02 , H01F41/04 , H05K1/16 , H02M3/00 , H01F17/00 , H05K1/03 , H02M1/00
Abstract: A switched inductor DC-DC power converter chiplet includes a CMOS power switch, an LC filter, regulation circuitry, feedback control circuitry, and interface control circuitry integrated on a common substrate. The inductor for the LC filter can be formed on the same surface or on opposing surfaces of the substrate as the electrical terminations for the substrate. Another embodiment includes a switched inductor DC-DC power converter chiplet having a first powertrain phase and multiple second powertrain phases. When the load current is less than or equal to a threshold load current, the power conversion efficiency can be improved by only operating the first powertrain phase. When the load current is greater than the threshold load current, the power conversion efficiency can be improved by operating one or more second powertrain phases.
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Patent Agency Ranking
公开(公告)号：US09906131B1
公开(公告)日：2018-02-27
申请号：US15243022
申请日：2016-08-22
Applicant: Ferric Inc.
Inventor： William Lee , David Jew , Joseph Meyer , Noah Sturcken
CPC classification number: H02M3/158 , H02M1/38 , H02M3/157 , H02M3/1588 , H02M2001/0058 , Y02B70/1491
Abstract: A switched-mode power converter includes timing control feedback loop circuits to minimize or eliminate the potential difference across a high-power switch and a low-power switch during their transitions times. A first feedback circuit compares the measured voltage across the high-power switch at the moment the high-power switch closes with the input voltage to the high-power switch to control a low-to-high delay time. A second feedback circuit compares the measured voltage across the low-power switch at the moment the low-power switch closes with the input voltage to the low-power switch to control a high-to-low delay time. A third feedback circuit compares the measured voltage across the low-power switch at the moment the low-power switch opens. The output of the third feedback circuit is provided as inputs to the first and second feedback circuits. The third feedback circuit also controls the frequency of the power converter.
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公开(公告)号：US20180054118A1
公开(公告)日：2018-02-22
申请号：US15243022
申请日：2016-08-22
Applicant: Ferric Inc.
Inventor： William Lee , David Jew , Joseph Meyer , Noah Sturcken
CPC classification number: H02M3/158 , H02M1/38 , H02M3/157 , H02M3/1588 , H02M2001/0058 , Y02B70/1491
Abstract: A switched-mode power converter includes timing control feedback loop circuits to minimize or eliminate the potential difference across a high-power switch and a low-power switch during their transitions times. A first feedback circuit compares the measured voltage across the high-power switch at the moment the high-power switch closes with the input voltage to the high-power switch to control a low-to-high delay time. A second feedback circuit compares the measured voltage across the low-power switch at the moment the low-power switch closes with the input voltage to the low-power switch to control a high-to-low delay time. A third feedback circuit compares the measured voltage across the low-power switch at the moment the low-power switch opens. The output of the third feedback circuit is provided as inputs to the first and second feedback circuits. The third feedback circuit also controls the frequency of the power converter.
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4.发明申请公开(公告)号：US20190182957A1
公开(公告)日：2019-06-13
申请号：US16279574
申请日：2019-02-19
Applicant: Ferric Inc.
Inventor： Noah Sturcken , Joseph Meyer , Michael Lekas , Ryan Davies , David Jew , William Lee
Abstract: A switched inductor DC-DC power converter chiplet includes a CMOS power switch, an LC filter, regulation circuitry, feedback control circuitry, and interface control circuitry integrated on a common substrate. The inductor for the LC filter can be formed on the same surface or on opposing surfaces of the substrate as the electrical terminations for the substrate. Another embodiment includes a switched inductor DC-DC power converter chiplet having a first powertrain phase and multiple second powertrain phases. When the load current is less than or equal to a threshold load current, the power conversion efficiency can be improved by only operating the first powertrain phase. When the load current is greater than the threshold load current, the power conversion efficiency can be improved by operating one or more second powertrain phases.
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公开(公告)号：US10326366B2
公开(公告)日：2019-06-18
申请号：US15869726
申请日：2018-01-12
Applicant: Ferric Inc.
Inventor： William Lee , David Jew , Joseph Meyer , Noah Sturcken
Abstract: A switched-mode power converter includes timing control feedback loop circuits to minimize or eliminate the potential difference across a high-power switch and a low-power switch during their transitions times. A first feedback circuit compares the measured voltage across the high-power switch at the moment the high-power switch closes with the input voltage to the high-power switch to control a low-to-high delay time. A second feedback circuit compares the measured voltage across the low-power switch at the moment the low-power switch closes with the input voltage to the low-power switch to control a high-to-low delay time. A third feedback circuit compares the measured voltage across the low-power switch at the moment the low-power switch opens. The output of the third feedback circuit is provided as inputs to the first and second feedback circuits. The third feedback circuit also controls the frequency of the power converter.
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公开(公告)号：US20180145592A1
公开(公告)日：2018-05-24
申请号：US15869726
申请日：2018-01-12
Applicant: Ferric Inc.
Inventor： William Lee , David Jew , Joseph Meyer , Noah Sturcken
CPC classification number: H02M3/158 , H02M1/38 , H02M3/157 , H02M3/1588 , H02M2001/0058 , Y02B70/1466 , Y02B70/1491
Abstract: A switched-mode power converter includes timing control feedback loop circuits to minimize or eliminate the potential difference across a high-power switch and a low-power switch during their transitions times. A first feedback circuit compares the measured voltage across the high-power switch at the moment the high-power switch closes with the input voltage to the high-power switch to control a low-to-high delay time. A second feedback circuit compares the measured voltage across the low-power switch at the moment the low-power switch closes with the input voltage to the low-power switch to control a high-to-low delay time. A third feedback circuit compares the measured voltage across the low-power switch at the moment the low-power switch opens. The output of the third feedback circuit is provided as inputs to the first and second feedback circuits. The third feedback circuit also controls the frequency of the power converter.
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