公开(公告)号：US10716209B2

公开(公告)日：2020-07-14

申请号：US16565639

申请日：2019-09-10

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Eng Huat Goh ,  Jackson Chung Peng Kong ,  Khang Choong Yong ,  Min Suet Lim

IPC: H05K1/11 ,  H05K3/40 ,  H05K1/03 ,  H05K3/46

Abstract: To overcome the problem of the fiber weave effect desynchronizing differential signals in a pair of traces of approximately the same length in a printed circuit board, the pair of traces can be routed to traverse largely parallel paths that are above one another in the printed circuit board. The material between the paths can include weaved fiber bundles. The material on opposite sides of the paths, surrounding the pair of traces and the weaved fiber bundles, can include resin-rich material. As a result, the pair of traces are directly adjacent to the same materials, which can allow signals in the traces to propagate at the same speed, and prevent desynchronization of differential signals traversing the paths. The path length difference associated with traversing to different depths can be compensated with a relatively small in-plane diagonal jog of one of the traces.

公开(公告)号：US20190221529A1

公开(公告)日：2019-07-18

申请号：US15869992

申请日：2018-01-12

Applicant: Intel Corporation

Inventor： Khang Choong Yong ,  Boon Ping Koh ,  Eng Huat Goh ,  Min Suet Lim ,  Wil Choon Song

IPC: H01L23/66 ,  H01L23/552 ,  H01L23/24 ,  H01L21/48 ,  H01L25/18 ,  H01Q1/52 ,  H01Q1/22

CPC classification number: H01L23/66 ,  H01L21/481 ,  H01L21/4853 ,  H01L23/24 ,  H01L23/552 ,  H01L23/562 ,  H01L25/18 ,  H01L2223/6677 ,  H01Q1/2283 ,  H01Q1/44 ,  H01Q1/526 ,  H01Q7/00 ,  H04B15/02

Abstract: Described herein are microelectronics packages and methods for manufacturing the same. The microelectronics package may include a transmitter, a receiver, and a package stiffening element. The package stiffening element may be in electrical communication with the transmitter and the receiver. The package stiffening element may be configured to act as an antenna for both the transmitter and the receiver.

公开(公告)号：US20190103357A1

公开(公告)日：2019-04-04

申请号：US15720393

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Eng Huat Goh ,  Khang Choong Yong ,  Wil Choon Song ,  Jiun Hann Sir ,  Boon Ping Koh

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/065 ,  H01L23/498 ,  B81C1/00 ,  H01L23/48 ,  H01L23/00

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a first package, wherein the first package includes a first substrate section and a second substrate section. A plurality of stacked die may be disposed between the first substrate section and the second substrate section, wherein a surface of a first die of the plurality of stacked die is coplanar with a surface of the first section and with a surface of the second section. A second package is physically and electrically coupled to the first package.

公开(公告)号：US20190008052A1

公开(公告)日：2019-01-03

申请号：US16003970

申请日：2018-06-08

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Min Suet Lim ,  Tin Poay Chuah ,  Han Kung Chua

IPC: H05K3/46 ,  H05K1/02 ,  H05K1/18 ,  H05K3/30

Abstract: Disclosed herein is a multi-planar circuit board, as well as related structures and methods. In an embodiment, a circuit board may include a first surface, a first section having the first surface in a first plane, a second section having the first surface in a second plane, and a third section connecting the first and second sections, where the third section defines a gradient between the first and second planes, and where all sections are sections within a contiguous board. In another embodiment, circuit board may further include a first component having a first thickness coupled on the first face of the first section, and a second component having a second thickness, greater than the first component, coupled on the first face of the second section, where the second section is in a lower plane, and where the overall thickness is the circuit board thickness plus the second thickness.

公开(公告)号：US20180175002A1

公开(公告)日：2018-06-21

申请号：US15380669

申请日：2016-12-15

Applicant: Intel Corporation

Inventor： Howe Yin Loo ,  Eng Huat Goh ,  Min Suet Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Khang Choong Yong

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652

Abstract: A system-in-package apparatus includes a package substrate configured to carry at least one semiconductive device on a die side and a package bottom interposer disposed on the package substrate on a land side. A land side board mates with the package bottom interposer, and enough vertical space is created by the package bottom interposer to allow space for at least one device disposed on the package substrate on the land side.

公开(公告)号：US20180145051A1

公开(公告)日：2018-05-24

申请号：US15357233

申请日：2016-11-21

Applicant: Intel Corporation

Inventor： Howe Yin Loo ,  Eng Huat Goh ,  Min Suet Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Khang Choong Yong

IPC: H01L25/065 ,  H01L25/16 ,  H01L25/00 ,  H01L23/498 ,  H05K1/11 ,  H05K3/36 ,  H05K3/30

CPC classification number: H01L25/0657 ,  H01L23/49811 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311 ,  H05K1/111 ,  H05K1/141 ,  H05K3/30 ,  H05K3/36 ,  H05K3/368 ,  H05K2201/042 ,  H05K2201/10015 ,  H05K2201/1003 ,  H05K2201/10159 ,  H05K2201/10378 ,  H05K2201/10545 ,  H05K2201/10734

Abstract: A system-in-package apparatus includes a package substrate configured to carry at least one semiconductive device on a die side and a through-mold via package bottom interposer disposed on the package substrate on a land side. A land side board mates with the through-mold via package bottom interposer, and enough vertical space is created by the through-mold via package bottom interposer to allow space for at least one device disposed on the package substrate on the land side.

公开(公告)号：US09893444B2

公开(公告)日：2018-02-13

申请号：US14863974

申请日：2015-09-24

Applicant: INTEL CORPORATION

Inventor： Jackson Chung Peng Kong ,  Eng Huat Goh ,  Bok Eng Cheah ,  Su Sin Florence Phun ,  Khang Choong Yong ,  Min Keen Tang

IPC: H01R12/73 ,  H01R12/72 ,  C25D7/00 ,  C25D5/34 ,  C25D5/48 ,  H01R13/66 ,  H05K3/00 ,  H01G4/06 ,  H01G4/228 ,  H01G4/40

CPC classification number: H01R12/721 ,  C23C18/1653 ,  C25D5/34 ,  C25D5/48 ,  C25D7/00 ,  H01G4/06 ,  H01G4/228 ,  H01G4/40 ,  H01R12/732 ,  H01R13/6625 ,  H05K1/117 ,  H05K1/162 ,  H05K3/00 ,  H05K2201/0187

Abstract: A board-edge interconnection module features integrated capacitive coupling, which enables a board design employing the module to avoid having AC capacitors and flexible cables with bulky connectors. The recovered real estate enables further miniaturization, enabling the component to be used on a wide variety of devices, including ultra-mobile computing devices.

公开(公告)号：US09613920B2

公开(公告)日：2017-04-04

申请号：US14986542

申请日：2015-12-31

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Hoay Tien Teoh

IPC: H01L23/00 ,  H01L21/50 ,  H01L23/48 ,  H01L23/29 ,  H01L23/538 ,  H01L21/768 ,  H01L23/31

CPC classification number: H01L24/02 ,  H01L21/50 ,  H01L21/76898 ,  H01L23/295 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L2224/02311 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05024 ,  H01L2224/05567 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/2518 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/0105 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A microelectronic package having a first bumpless build-up layer structure adjacent an active surface and sides of a microelectronic device and a second bumpless build-up layer structure adjacent a back surface of the microelectronic device, wherein conductive routes are formed through the first bumpless build-up layer from the microelectronic device active surface to conductive routes in the second bumpless build-up layer structure and wherein through-silicon vias adjacent the microelectronic device back surface and extending into the microelectronic device are electrically connected to the second bumpless build-up layer structure conductive routes.

公开(公告)号：US20250113428A1

公开(公告)日：2025-04-03

申请号：US18478967

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Eng Huat Goh ,  Tin Poay Chuah ,  Kavitha Nagarajan ,  Telesphor Kamgaing ,  Poh Boon Khoo ,  Jiun Hann Sir

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/34 ,  H05K3/40

Abstract: Technologies for a shield for electromagnetic interference include a circuit board with an integrated circuit package on it, with a hole in the circuit board under the integrated circuit package. The integrated circuit package may include one or more dies or other components on the underside of the package, at least partially positioned in the hole in the circuit board. An electromagnetic shield box can be positioned in the hole. Tabs of the electromagnetic shield box may interface with pads on the same side of the circuit board as the integrated circuit package. The electromagnetic shield box may prevent or reduce electromagnetic or radiofrequency interference on the components of the integrated circuit package. Positioning the electromagnetic shield box can reduce the overall height of the circuit board, among other advantages.

公开(公告)号：US20250052512A1

公开(公告)日：2025-02-13

申请号：US18447951

申请日：2023-08-10

Applicant: Intel Corporation

Inventor： Shantanu Kulkarni ,  Jeff Ku ,  Baomin Liu ,  Tongyan Zhai ,  Min Suet Lim ,  Chee Chun Yee ,  Eng Huat Goh ,  Jun Liao ,  Kavitha Nagarajan

IPC: F28D15/04

Abstract: Systems, apparatus, articles of manufacture, and methods related to multi-sectional vapor chambers for electronic devices are disclosed. An example vapor chamber includes a first panel, a second panel, and a wall extending between the first panel and the second panel to separate the vapor chamber into a first section and a second section between both the first panel and the second panel, the wall including insulation.