公开(公告)号：US10191759B2

公开(公告)日：2019-01-29

申请号：US15025735

申请日：2013-11-27

Applicant: INTEL CORPORATION

Inventor： David J. Cowperthwaite ,  Murali Ramadoss ,  Ankur N. Shah ,  Balaji Vembu ,  Altug Koker ,  Aditya Navale

IPC: G06F9/455 ,  G06F9/50 ,  G06T1/20

Abstract: In an embodiment, a system includes a graphics processing unit (GPU) that includes one or more GPU engines, and a microcontroller. The microcontroller is to assign a respective schedule slot for each of a plurality of virtual machines (VMs). When a particular VM is scheduled to access a first GPU engine, the particular VM has exclusive access to the first GPU engine. Other embodiments are described and claimed.

公开(公告)号：US10078879B2

公开(公告)日：2018-09-18

申请号：US14692984

申请日：2015-04-22

Applicant: INTEL CORPORATION

Inventor： Hema Chand Nalluri ,  Aditya Navale

IPC: G09G5/36 ,  G06T1/20 ,  G06F9/52 ,  G09G5/00

CPC classification number: G06T1/20 ,  G06F9/48 ,  G06F9/52 ,  G06F15/167 ,  G09G5/001

Abstract: Memory-based semaphores are described that are useful for synchronizing processes between different processing engines. In one example, operations include executing a first process at a first processing engine, the executing including updating a memory register, sending a signal from the first processing engine to a second processing engine that the memory register has been updated, the signal including a memory register address to identify the updated memory register inline data and a dataword, fetching data from the memory register by the second processing engine, comparing the fetched data to the received dataword, and conditionally executing a next command of a second process at the second processing engine based on the comparison.

公开(公告)号：US09633230B2

公开(公告)日：2017-04-25

申请号：US13649798

申请日：2012-10-11

Applicant: INTEL CORPORATION

Inventor： Hema C. Nalluri ,  Aditya Navale ,  Murali Ramadoss

IPC: G06F21/74 ,  G06F21/84 ,  G06T15/00

CPC classification number: G06F21/74 ,  G06F21/84 ,  G06T15/005

Abstract: Techniques are disclosed for processing rendering engine workload of a graphics system in a secure fashion, wherein at least some security processing of the workload is offloaded from software-based security parsing to hardware-based security parsing. In some embodiments, commands from a given application are received by a user-mode driver (UMD), which is configured to generate a command buffer delineated into privileged and/or non-privileged command sections. The delineated command buffer can then be passed by the UMD to a kernel-mode driver (KMD), which is configured to parse and validate only privileged buffer sections, but to issue all other batch buffers with a privilege indicator set to non-privileged. A graphics processing unit (GPU) can receive the privilege-designated batch buffers from the KMD, and is configured to disallow execution of any privileged command from a non-privileged batch buffer, while any privileged commands from privileged batch buffers are unrestricted by the GPU.

公开(公告)号：US09626732B2

公开(公告)日：2017-04-18

申请号：US14050626

申请日：2013-10-10

Applicant: Intel Corporation

Inventor： Hema C. Nalluri ,  Aditya Navale ,  Altug Koker

IPC: G06F15/80 ,  G06T1/20

CPC classification number: G06T1/20

Abstract: Methods and systems may provide for storing a set of post-synchronization operations to a graphics memory and sending a flush marker to a graphics pipeline. Additionally, the set of post-synchronization operations may be processed in response to the flush marker exiting the graphics pipeline. In one example, the set of post-synchronization operations includes one or more atomic operations. Moreover, the set of post-synchronization operations may be obtained from an inline portion of an atomics command.

公开(公告)号：US09223603B2

公开(公告)日：2015-12-29

申请号：US13932963

申请日：2013-07-01

Applicant: INTEL CORPORATION

Inventor： Balaji Vembu ,  Aditya Navale ,  Wishwesh Gandhi

IPC: G09G5/39 ,  G06F9/455 ,  G06F9/44 ,  G06F12/10 ,  G06F13/28 ,  G06T1/60

CPC classification number: G06F12/1009 ,  G06F9/4401 ,  G06F9/4403 ,  G06F9/4411 ,  G06F9/45533 ,  G06F9/45558 ,  G06F12/109 ,  G06F13/28 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06F2212/152 ,  G06T1/60

Abstract: A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating GPAs of graphics data direct memory access (DMA) requests of a computing environment implementing a virtual machine monitor to support virtual machines. The requests may be sent through a render or display path of the computing environment from one or more virtual machines, transparently with respect to the virtual machine monitor. The creating, updating, and using may be performed by a memory controller detecting entries sent to existing global and page directory tables, forking off shadow table entries from the detected entries, and translating GPAs to HPAs for the shadow table entries.

Abstract translation: 一种用于创建，更新和使用访客物理地址（GPA）以主机物理地址（HPA）影子转换表的方法和装置，用于将实现虚拟机监视器的计算环境的图形数据直接存储器访问（DMA）请求的GPA转换为 支持虚拟机。 可以通过虚拟机监视器透明地从一个或多个虚拟机通过计算环境的呈现或显示路径发送请求。 创建，更新和使用可以由存储器控制器执行，该存储器控制器检测发送到现有全局和页目录表的条目，从检测到的条目中分离影子表条目，以及将影子表条目的GPA转换为HPA。

公开(公告)号：US20230109990A1

公开(公告)日：2023-04-13

申请号：US17496467

申请日：2021-10-07

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Altug Koker ,  Aditya Navale ,  Prasoonkumar Surti ,  Ankur Shah ,  Joydeep Ray ,  Naveen Matam

IPC: G06T1/20

Abstract: One embodiment provides a graphics processor including an active base die including a fabric interconnect and a chiplet including a switched fabric, wherein the chiplet couples with the active base die via an array of interconnect structures, the array of interconnect structures couple the fabric interconnect with the switched fabric, and the chiplet includes a first modular interconnect configured to couple a block of graphics processing resources to the switched fabric and a second modular interconnect configured to couple a memory subsystem with the switched fabric and the block of graphics processing resources, the memory interconnect including a set of memory controllers and a set of physical interfaces.

公开(公告)号：US20230094002A1

公开(公告)日：2023-03-30

申请号：US17484711

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Hema Chand Nalluri ,  Jeffery S. Boles ,  Joseph Koston ,  Ankur N. Shah ,  Vidhya Krishnan ,  Vasanth Ranganathan ,  Joydeep Ray ,  Aditya Navale ,  Murali Ramadoss ,  James Valerio

IPC: G06F9/48 ,  G06T1/20

Abstract: Dynamic routing of texture-load in graphics processing is described. An example of an apparatus includes a graphics processor including a plurality of processing engines of a class of processing engines of the graphic processor; a set of queues for the plurality of processing engines; and a unified submit port for the plurality of processing engines, wherein the unified submit port is to notify a scheduler regarding availability of slots in the set of queues for receipt of workload contexts; and wherein, upon the unified submit port receiving a workload context for processing by the plurality of processing engines, the unified submit port is to detect an available processing engine of the plurality of processing engines and direct the received context to a slot of the set of queues for processing by the available processing engine.

公开(公告)号：US11556480B2

公开(公告)日：2023-01-17

申请号：US17246954

申请日：2021-05-03

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Altug Koker ,  Aditya Navale ,  Ankur Shah ,  Murali Ramadoss ,  Ben Ashbaugh ,  Ronald Silvas

IPC: G06F12/10 ,  G06F12/1072

Abstract: Systems and methods for providing shared virtual memory addressing support for a host system are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations. A memory management unit (MMU) is coupled to the processing resources. The MMU to support a first virtual address size for managing allocation of non-shared virtual memory and to support a second virtual address size for managing allocation of shared virtual memory that is shared between the graphics processor and a host.

公开(公告)号：US20210407194A1

公开(公告)日：2021-12-30

申请号：US16914783

申请日：2020-06-29

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Saurabh Sharma ,  Jorge F. Garcia Pabon ,  Raghavendra Kamath Miyar ,  Sudheendra Srivathsa ,  Justin Decell ,  Aditya Navale

IPC: G06T17/20 ,  G06T15/00 ,  G06T1/20

Abstract: An apparatus to facilitate graphics rendering is disclosed. The apparatus comprises sequencer hardware to operate in a tile mode to render objects, including performing batch formation to generate one or more batches of received objects, performing tile sequencing for each of the objects to compute tile fill intersects for each of the objects and performing a play sequencing of each of the objects.

公开(公告)号：US11157431B2

公开(公告)日：2021-10-26

申请号：US16447025

申请日：2019-06-20

Applicant: Intel Corporation

Inventor： Bryan R. White ,  Aravindh Anantaraman ,  Ankur Shah ,  Altug Koker ,  David Puffer ,  Aditya Navale

IPC: G06F13/36 ,  G06F13/40 ,  G06T1/20 ,  G06F13/42

Abstract: In one embodiment, a method includes: receiving, in a root tile of an accelerator device having a plurality of tiles, a message from a processor, the message comprising a register write request to a register of a first remote tile of the plurality of remote tiles; decoding, in an endpoint controller of the root tile, a system address of the message to identify a destination tile for the message, based at least in part on a base address register decode of the system address; and in response to identifying the first remote tile as the destination tile, updating a first portion of an address offset field of the system address to a predetermined value and directing the message to the first remote tile coupled to the root tile via a sideband interconnect. Other embodiments are described and claimed.