公开(公告)号：US20160077569A1

公开(公告)日：2016-03-17

申请号：US14484649

申请日：2014-09-12

Applicant: Intel Corporation

Inventor： Yoni Aizik ,  Eliezer Weissmann ,  Efraim Rotem ,  Yevgeni Sabin ,  Doron Rajwan ,  Ahmad Yasin

IPC: G06F1/32 ,  G06F1/28

CPC classification number: G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: In an embodiment, a processor includes at least one core and energy performance gain (EPG) logic to determine an EPG frequency based on a first value of an EPG. The EPG is based upon energy consumed by the processor and upon performance of the processor. The processor also includes a clock generator to generate a frequency of operation of the at least one core based on the EPG frequency. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括至少一个核心和能量性能增益（EPG）逻辑，以基于EPG的第一值来确定EPG频率。 EPG基于处理器消耗的能量和处理器的性能。 处理器还包括时钟发生器，用于基于EPG频率产生至少一个核心的操作频率。 描述和要求保护其他实施例。

公开(公告)号：US09098415B2

公开(公告)日：2015-08-04

申请号：US13691016

申请日：2012-11-30

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC: G06F3/00 ,  G06F13/14 ,  G06F12/08 ,  G06F1/32 ,  H04L12/66 ,  G06F13/40 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract translation: 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

公开(公告)号：US20150149683A9

公开(公告)日：2015-05-28

申请号：US13691016

申请日：2012-11-30

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC: G06F13/40

CPC classification number: G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract translation: 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

公开(公告)号：US20140344598A1

公开(公告)日：2014-11-20

申请号：US14451807

申请日：2014-08-05

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Inder M. Sodhi ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Ryan Wells

IPC: G06F1/32 ,  G11C7/22

CPC classification number: G06F1/324 ,  G06F1/3203 ,  G06F1/3293 ,  G06F1/3296 ,  G06F13/4068 ,  G06F13/4282 ,  G11C7/22 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/151

Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有多个域的处理器，至少包括对于操作系统（OS）是透明的核心域和非核心域。 非核心域可以由驱动程序控制。 反过来，处理器还包括将核心域和非核心域互连到耦合到处理器的存储器的存储器互连。 此外，可以在处理器内的功率控制器可以基于在非核域上执行的工作负载的存储器有界性来控制存储器互连的频率。 描述和要求保护其他实施例。

公开(公告)号：US08775833B2

公开(公告)日：2014-07-08

申请号：US13780066

申请日：2013-02-28

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Nadav Shulman

IPC: G06F1/00 ,  G06F15/00 ,  G05D3/12

CPC classification number: G06F1/26 ,  G06F1/3243 ,  G06F9/5094 ,  Y02D10/152

Abstract: In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed.

公开(公告)号：US11899599B2

公开(公告)日：2024-02-13

申请号：US17527929

申请日：2021-11-16

Applicant: INTEL CORPORATION

Inventor： Eliezer Weissmann ,  Efraim Rotem ,  Doron Rajwan ,  Hisham Abu Salah ,  Ariel Gur ,  Guy M. Therien ,  Russell J. Fenger

IPC: G06F13/24 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/30 ,  G06F1/3234 ,  G06F9/44 ,  G06F9/4401

CPC classification number: G06F13/24 ,  G06F1/329 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/44 ,  G06F9/4411

Abstract: Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.

公开(公告)号：US11815979B2

公开(公告)日：2023-11-14

申请号：US16633120

申请日：2017-08-22

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Yoni Aizik ,  Esfir Natanzon ,  Nir Rosenzweig ,  Nadav Shulman ,  Bart Plackle

IPC: G06F1/329 ,  G06F9/48

CPC classification number: G06F1/329 ,  G06F9/4893

Abstract: Embodiments include apparatuses, methods, and systems including a power control unit to control different power consumptions by one or more processors to operate different applications. The power control unit may receive power information that may include a priority information for each application to be operated on the one or more processors, determine to control, based on the power information for different applications, different power consumptions by the one or more processors to operate the different applications. Other embodiments may also be described and claimed.

公开(公告)号：US20220374278A1

公开(公告)日：2022-11-24

申请号：US17882175

申请日：2022-08-05

Applicant: Intel Corporation

Inventor： Toby Opferman ,  Eliezer Weissmann ,  Robert Valentine ,  Russell Cameron Arnold

IPC: G06F9/50 ,  G06F9/38 ,  G06F9/48 ,  G06F9/30 ,  G06F9/448

Abstract: The present disclosure relates to a processor that includes one or more processing elements associated with one or more instruction set architectures. The processor is configured to receive a request from an application executed by a first processing element of the one or more processing elements to enable a feature associated with an instruction set architecture. Additionally, the processor is configured to enable the application to utilize the feature without a system call occurring when the feature is associated with an instruction set architecture associated with the first processing element.

公开(公告)号：US11221857B2

公开(公告)日：2022-01-11

申请号：US16388670

申请日：2019-04-18

Applicant: Intel Corporation

Inventor： Guy M. Therien ,  Paul S. Diefenbaugh ,  Anil Aggarwal ,  Andrew D. Henroid ,  Jeremy J. Shrall ,  Efraim Rotem ,  Krishnakanth V. Sistla ,  Eliezer Weissmann

IPC: G06F1/00 ,  G06F11/30 ,  G06F9/4401 ,  G06F16/22 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/44 ,  G06F9/445 ,  G06F1/28 ,  G06F1/3234 ,  G06F11/36 ,  G06F1/26 ,  G06F9/22 ,  G06F11/34 ,  G06F9/30 ,  G06F1/20 ,  G06F15/78 ,  G06F1/32 ,  G06F9/38 ,  G06F119/06

Abstract: The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.

公开(公告)号：US11182315B2

公开(公告)日：2021-11-23

申请号：US15430345

申请日：2017-02-10

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Efraim Rotem ,  Doron Rajwan ,  Hisham Abu Salah ,  Ariel Gur ,  Guy M. Therien ,  Russell J. Fenger

IPC: G06F13/24 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/30 ,  G06F9/44 ,  G06F9/4401 ,  G06F1/3234

Abstract: Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.