公开(公告)号：US20250079398A1

公开(公告)日：2025-03-06

申请号：US18460817

申请日：2023-09-05

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Wilfred Gomes ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Pushkar Sharad Ranade ,  Nitin A. Deshpande ,  Abhishek A. Sharma

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H10B80/00

Abstract: Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including conductive traces that are parallel to the first and second surfaces and exposed at the third surface; a second IC die having a fourth surface and including voltage regulator circuitry; and a third IC die having a fifth surface, wherein the third surface of the first IC die is electrically coupled to the fifth surface of the third IC die by first interconnects, the fourth surface of the second IC die is electrically coupled to the fifth surface of the third IC die by second interconnects, and the first IC die is electrically coupled to the second IC die by conductive pathways in the third IC die.

公开(公告)号：US20240222328A1

公开(公告)日：2024-07-04

申请号：US18148543

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Wilfred Gomes ,  Nisha Ananthakrishnan ,  Kemal Aygun ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10B12/00

CPC classification number: H01L25/0657 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53295 ,  H10B12/39

Abstract: Embodiments of a microelectronic assembly include: a first integrated circuit (IC) die having a first memory circuit and a second memory circuit, a second IC die; a third IC die; and a package substrate. The first IC die comprises: a first portion comprising a first active region and a first backend region in contact with the first active region; and a second portion comprising a second active region and a second backend region in contact with the second active region. The second portion is surrounded by the first portion in plan view, the first memory circuit is in the first portion, the second memory circuit is in the second portion, the first active region comprises transistors that are larger than transistors in the second active region, and the first backend region comprises conductive traces that have a larger pitch than conductive traces in the second backend region.

公开(公告)号：US20240105677A1

公开(公告)日：2024-03-28

申请号：US17955269

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Tahir Ghani ,  Sagar Suthram ,  Anand Murthy ,  Wilfred Gomes ,  Pushkar Ranade

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/427 ,  H01L25/00

CPC classification number: H01L25/0655 ,  H01L23/427 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L24/32 ,  H01L2224/08145 ,  H01L2224/32221 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: An integrated circuit device includes a first IC die with a first front surface, a first back surface, and a first side surface along opposed edges of the first front surface and the first back surfaces of the first IC die, a second IC die with a second front surface, a second back surface, and a second side surface along opposed edges of the second front surface and second back surface of the second IC die, a substrate coupled to the first side surface of the first IC die and the second side surface of the second IC die, and fill material between one of the first front surface and the first back surface of the first IC die and one of the second front surface and second back surface of the second IC die. Other embodiments are disclosed and claimed.

公开(公告)号：US20240105584A1

公开(公告)日：2024-03-28

申请号：US17955203

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Tahir Ghani ,  Anand Murthy ,  Wilfred Gomes ,  Sagar Suthram ,  Pushkar Ranade

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5223 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226

Abstract: An integrated circuit (IC) die includes a plurality of front-side metallization layers including a first front-side metallization layer and one or more additional front-side metallization layers, a plurality of back-side metallization layers formed on the plurality front side metallization layers including a first back-side metallization layer and one or more additional back-side metallization layers, wherein the first front-side metallization layer is proximate to the first back-side metallization layer, and a vertical metallization structure formed through at least the first front-side metallization layer and the first back-side metallization layer, wherein the vertical metallization structure electrically connects a first metallization structure on one of the one or more additional front-side metallization layers to a second metallization structure on one of the one or more additional back-side metallization layers. Other embodiments are disclosed and claimed.

公开(公告)号：US20240105582A1

公开(公告)日：2024-03-28

申请号：US17955262

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Tahir Ghani ,  Anand Murthy ,  Wilfred Gomes ,  Sagar Suthram ,  Pushkar Ranade

IPC: H01L23/522 ,  H01L23/473 ,  H01L23/50

CPC classification number: H01L23/5222 ,  H01L23/473 ,  H01L23/50

Abstract: An integrated circuit die includes a first conductive structure for an input of a capacitively coupled device, a second conductive structure aligned with the first conductive structure for a signal to be capacitively coupled to the input of the capacitively coupled device, a first insulator material disposed between the first conductive structure and the second conductive structure, wherein the first insulator material comprises high gain insulator material, and a cooling structure operable to remove heat from the capacitively coupled device to achieve an operating temperature at or below 0° C. Other embodiments are disclosed and claimed.

公开(公告)号：US20240088017A1

公开(公告)日：2024-03-14

申请号：US17930825

申请日：2022-09-09

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Tahir Ghani ,  Wilfred Gomes ,  Anand S. Murthy ,  Pushkar Sharad Ranade ,  Sagar Suthram

IPC: H01L23/522 ,  H01L21/768 ,  H01L49/02

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40

Abstract: Described herein are full wafer devices that include passive devices formed in one or more interconnect layers. Interconnect layers are formed over a front side of the full wafer device. A passive device is formed using an additive process that results in a seam running through the passive device. The seam may be, for example, an air gap, a change in material structure, or a region with a different chemical makeup from the surrounding passive device. In some embodiments, the passive devices are formed in global interconnect layers coupling multiple does of the full wafer device.

公开(公告)号：US20240071955A1

公开(公告)日：2024-02-29

申请号：US17899670

申请日：2022-08-31

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Tahir Ghani ,  Wilfred Gomes ,  Shem Ogadhoh ,  Swaminathan Sivakumar ,  Sagar Suthram ,  Elliot Tan

IPC: H01L23/00 ,  H01L23/528 ,  H01L27/085

CPC classification number: H01L23/564 ,  H01L23/528 ,  H01L27/085

Abstract: Described herein is full wafer device that includes a computing logic formed over a substrate and two directional indicators formed in the substrate. The computing logic is arranged as a plurality of dies having a first die edge direction and a second die edge direction perpendicular to the first die edge direction. The computing logic further includes an angled feature extending in a feature direction, the feature direction different from the first die edge direction and the second die edge direction. The first directional indicator formed in the substrate indicates the first die edge direction. The second directional indicator formed in the substrate indicates the feature direction.

公开(公告)号：US20240008286A1

公开(公告)日：2024-01-04

申请号：US17856878

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Wilfred Gomes ,  Anand Murthy ,  Sagar Suthram ,  Tahir Ghani

IPC: H01L27/11514 ,  H01L29/78 ,  H01L29/66 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/11514 ,  H01L29/78391 ,  H01L29/6684 ,  H01L23/5226 ,  H01L23/5283

Abstract: Bits are stored in an array with multiple storage elements sharing a single access transistor and a storage line coupled to the transistor. A single common select transistor accesses information stored in an array of storage elements. Other arrays of storage elements on parallel storage lines can be coupled into a crosspoint array by source lines orthogonal to the storage lines. The storage elements may be non-volatile. In an integrated circuit system, the array may be coupled to a power supply and a cooling structure.

公开(公告)号：US20240008259A1

公开(公告)日：2024-01-04

申请号：US17856868

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Tahir Ghani ,  Anand Murthy ,  Wilfred Gomes ,  Sagar Suthram

IPC: H01L27/108

CPC classification number: H01L27/10826

Abstract: Integrated circuit dies, systems, and techniques are described herein related to three-dimensional dynamic random access memory. A memory device includes vertically aligned semiconductor structures coupled to independent gate structures, corresponding vertically aligned capacitors each coupled to a corresponding one of the semiconductor structures, and a bit line contact extending vertically across a depth of the semiconductor structures and coupled to each of the semiconductor structures.

公开(公告)号：US20240008239A1

公开(公告)日：2024-01-04

申请号：US17856870

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Wilfred Gomes ,  Tahir Ghani ,  Anand Murthy ,  Rajabali Koduri ,  Clifford Ong ,  Sagar Suthram

IPC: H01L27/11 ,  G11C11/412 ,  G11C11/419

CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/419

Abstract: Stacked static random-access memory (SRAM) circuits have doubled word length for a given SRAM cell area. An integrated circuit (IC) die includes stacked SRAM cells in vertically adjacent device layers with access transistors connected to a common wordline. The IC die with stacked SRAM cells having a common word line may be attached to a substrate and coupled to a power supply and, advantageously, to an active-cooling structure. SRAM cells may be formed in vertically adjacent layers of a substrate and electrically connected at their access transistor gate electrodes.